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//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.50  2004/04/26 15:26:23  igorm

// Revision 1.50  2004/04/26 15:26:23  igorm

// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the

// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the

//   previous update of the core.

//   previous update of the core.

// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.

// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.

// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER

// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER

wire     [7:0]  TxData;

wire     [7:0]  TxData;

wire            TxRetry;

wire            TxRetry;

wire            TxAbort;

wire            TxAbort;

wire            TxUnderRun;

wire            TxUnderRun;

wire            TxDone;

wire            TxDone;

reg             WillSendControlFrame_sync1;

reg             WillSendControlFrame_sync1;

reg             WillSendControlFrame_sync2;

reg             WillSendControlFrame_sync2;

reg             WillSendControlFrame_sync3;

reg             WillSendControlFrame_sync3;

wire        RxE_IRQ;        // Interrupt Rx Error

wire        RxE_IRQ;        // Interrupt Rx Error

wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)

wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)

//wire        DWord;

//wire        DWord;

wire        ByteSelected;

wire        ByteSelected;

wire        BDAck;

wire        BDAck;

wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)

wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)

wire  [3:0] BDCs;           // Buffer descriptor CS

wire  [3:0] BDCs;           // Buffer descriptor CS

wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set

wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set

                            // but data is not valid.

                            // but data is not valid.

reg CarrierSense_Tx2;

reg CarrierSense_Tx2;

reg Collision_Tx1;

reg Collision_Tx1;

reg Collision_Tx2;

reg Collision_Tx2;

reg RxEnSync;                 // Synchronized Receive Enable

reg RxEnSync;                 // Synchronized Receive Enable

reg WillTransmit_q;

reg WillTransmit_q;

reg WillTransmit_q2;

reg WillTransmit_q2;

// Synchronized Collision

// Synchronized Collision

assign Collision = ~r_FullD & Collision_Tx2;

assign Collision = ~r_FullD & Collision_Tx2;

// Delayed WillTransmit

// Delayed WillTransmit

always @ (posedge mrx_clk_pad_i)

always @ (posedge mrx_clk_pad_i)

begin

begin

  WillTransmit_q <= #Tp WillTransmit;

  WillTransmit_q <= #Tp WillTransmit;

  WillTransmit_q2 <= #Tp WillTransmit_q;

  WillTransmit_q2 <= #Tp WillTransmit_q;

always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)

always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)

begin

begin

  if(wb_rst_i)

  if(wb_rst_i)

    RxEnSync <= #Tp 1'b0;

    RxEnSync <= #Tp 1'b0;

  else

  else

  if(~mrxdv_pad_i)

  if(~mrxdv_pad_i)

    RxEnSync <= #Tp r_RxEn;

    RxEnSync <= #Tp r_RxEn;

end

end

wire LatchedMRxErr;

wire LatchedMRxErr;

reg RxAbort_latch;

reg RxAbort_latch;

reg RxAbort_sync1;

reg RxAbort_sync1;

reg RxAbort_wb;

reg RxAbort_wb;

reg RxAbortRst_sync1;

reg RxAbortRst_sync1;

reg RxAbortRst;

reg RxAbortRst;

// Synchronizing RxAbort to the WISHBONE clock

// Synchronizing RxAbort to the WISHBONE clock