| Line 277... |
Line 277... |
|
|
);
|
);
|
|
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
|
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH;
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|
|
|
|
// WISHBONE common
|
// WISHBONE common
|
input wb_clk_i; // WISHBONE clock
|
input wb_clk_i; // WISHBONE clock
|
input wb_rst_i; // WISHBONE reset
|
input wb_rst_i; // WISHBONE reset
|
| Line 381... |
Line 387... |
reg TxPauseRq_sync3;
|
reg TxPauseRq_sync3;
|
reg TPauseRq;
|
reg TPauseRq;
|
|
|
|
|
// Connecting Miim module
|
// Connecting Miim module
|
eth_miim miim1
|
eth_miim #(.Tp(Tp))
|
|
miim1
|
(
|
(
|
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
|
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
|
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
|
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
|
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
|
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
|
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
|
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
|
| Line 540... |
Line 547... |
end
|
end
|
`endif
|
`endif
|
|
|
|
|
// Connecting Ethernet registers
|
// Connecting Ethernet registers
|
eth_registers ethreg1
|
eth_registers #(.Tp(Tp))
|
|
ethreg1
|
(
|
(
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
| Line 597... |
Line 605... |
wire RetryLimit;
|
wire RetryLimit;
|
wire StatePreamble;
|
wire StatePreamble;
|
wire [1:0] StateData;
|
wire [1:0] StateData;
|
|
|
// Connecting MACControl
|
// Connecting MACControl
|
eth_maccontrol maccontrol1
|
eth_maccontrol #(.Tp(Tp))
|
|
maccontrol1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
|
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
| Line 650... |
Line 659... |
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
|
|
|
|
|
|
// Connecting TxEthMAC
|
// Connecting TxEthMAC
|
eth_txethmac txethmac1
|
eth_txethmac #(.Tp(Tp))
|
|
txethmac1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
|
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
| Line 684... |
Line 694... |
wire AddressMiss;
|
wire AddressMiss;
|
|
|
|
|
|
|
// Connecting RxEthMAC
|
// Connecting RxEthMAC
|
eth_rxethmac rxethmac1
|
eth_rxethmac #(.Tp(Tp))
|
|
rxethmac1
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
| Line 880... |
Line 891... |
end
|
end
|
|
|
|
|
|
|
// Connecting Wishbone module
|
// Connecting Wishbone module
|
eth_wishbone wishbone
|
eth_wishbone #(.Tp(Tp),
|
|
.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
|
.TX_FIFO_DEPTH (TX_FIFO_DEPTH),
|
|
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
|
|
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
|
.RX_FIFO_DEPTH (RX_FIFO_DEPTH),
|
|
.RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
|
|
wishbone
|
(
|
(
|
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
|
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
|
.WB_DAT_O(BD_WB_DAT_O),
|
.WB_DAT_O(BD_WB_DAT_O),
|
|
|
// WISHBONE slave
|
// WISHBONE slave
|
| Line 939... |
Line 957... |
);
|
);
|
|
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
|
|
|
// Connecting MacStatus module
|
// Connecting MacStatus module
|
eth_macstatus macstatus1
|
eth_macstatus #(.Tp(Tp))
|
|
macstatus1
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
|
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
