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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Diff between revs 251 and 257

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/11/19 17:37:32  mohor
 
// When control frame (PAUSE) was sent, status was written in the
 
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
 
// Only TXC interrupt is set.
 
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
//
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
Line 124... Line 129...
 
 
wire          IncrementDlyCrcCnt;
wire          IncrementDlyCrcCnt;
wire          ResetByteCnt;
wire          ResetByteCnt;
wire          IncrementByteCnt;
wire          IncrementByteCnt;
wire          ControlEnd;
wire          ControlEnd;
 
wire          IncrementByteCntBy2;
 
wire          EnableCnt;
 
 
 
 
// A command for Sending the control frame is active (latched)
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
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    BlockTxDone <= #Tp 1'b0;
    BlockTxDone <= #Tp 1'b0;
  else
  else
  if(TxCtrlStartFrm)
  if(TxCtrlStartFrm)
    BlockTxDone <= #Tp 1'b1;
    BlockTxDone <= #Tp 1'b1;
  else
  else
  if(TxDoneIn)
  if(TxStartFrmIn)
    BlockTxDone <= #Tp 1'b0;
    BlockTxDone <= #Tp 1'b0;
end
end
 
 
 
 
always @ (posedge MTxClk)
always @ (posedge MTxClk)
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end
end
 
 
 
 
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
 
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn;     // When TxUsedDataIn and CtrlMux are set at the same time
 
 
 
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    ByteCnt <= #Tp 6'h0;
    ByteCnt <= #Tp 6'h0;
  else
  else
  if(ResetByteCnt)
  if(ResetByteCnt)
    ByteCnt <= #Tp 6'h0;
    ByteCnt <= #Tp 6'h0;
  else
  else
  if(IncrementByteCnt & (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])))
  if(IncrementByteCntBy2 & EnableCnt)
 
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
 
  else
 
  if(IncrementByteCnt & EnableCnt)
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
end
 
 
 
 
assign ControlEnd = ByteCnt[5:0] == 6'h22;
assign ControlEnd = ByteCnt[5:0] == 6'h22;

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