OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 227 and 297

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 227 Rev 297
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.4  2002/10/18 17:04:20  tadejm
 
// Changed BIST scan signals.
 
//
// Revision 1.3  2002/10/10 16:29:30  mohor
// Revision 1.3  2002/10/10 16:29:30  mohor
// BIST added.
// BIST added.
//
//
// Revision 1.2  2002/09/23 18:24:31  mohor
// Revision 1.2  2002/09/23 18:24:31  mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
Line 146... Line 149...
      `endif
      `endif
      );
      );
 
 
`else   // !ETH_VIRTUAL_SILICON_RAM
`else   // !ETH_VIRTUAL_SILICON_RAM
 
 
 
`ifdef  ETH_ARTISAN_RAM
 
  `ifdef ETH_BIST
 
      art_hssp_256x32_bist ram0_bist
 
  `else
 
      art_hssp_256x32 ram0
 
  `endif
 
      (
 
        .CLK        (clk),
 
        .CEN        (!ce),
 
        .WEN        (!we),
 
        .OEN        (!oe),
 
        .A          (addr),
 
        .D          (di),
 
        .Q          (do)
 
 
 
      `ifdef ETH_BIST
 
        ,
 
        // debug chain signals
 
        .scanb_rst      (scanb_rst),
 
        .scanb_clk      (scanb_clk),
 
        .scanb_si       (scanb_si),
 
        .scanb_so       (scanb_so),
 
        .scanb_en       (scanb_en)
 
      `endif
 
      );
 
 
 
`else   // !ETH_ARTISAN_RAM
        //
        //
        // Generic single-port synchronous RAM model
        // Generic single-port synchronous RAM model
        //
        //
 
 
        //
        //
Line 189... Line 219...
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                        $display("Addr %h = %h",rnum,mem[rnum]);
                        $display("Addr %h = %h",rnum,mem[rnum]);
        end
        end
        endtask
        endtask
 
 
 
`endif  // !ETH_ARTISAN_RAM
`endif  // !ETH_VIRTUAL_SILICON_RAM
`endif  // !ETH_VIRTUAL_SILICON_RAM
`endif  // !ETH_XILINX_RAMB4
`endif  // !ETH_XILINX_RAMB4
 
 
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.