| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.8 2001/12/05 15:00:16 mohor
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// Revision 1.8 2001/12/05 15:00:16 mohor
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// instead of the number of RX descriptors).
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// instead of the number of RX descriptors).
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//
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//
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// Revision 1.7 2001/12/05 10:45:59 mohor
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// Revision 1.7 2001/12/05 10:45:59 mohor
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| Line 98... |
Line 101... |
// WISHBONE common
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// WISHBONE common
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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// WISHBONE slave
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_req_o, wb_ack_i, wb_nd_o, wb_rd_o,
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wb_ack_i,
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`ifdef WISHBONE_DMA
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wb_req_o, wb_nd_o, wb_rd_o,
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`else
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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`endif
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//TX
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//TX
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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//RX
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//RX
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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RxAbort,
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// MIIM
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// MIIM
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mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
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mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
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int_o
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int_o
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| Line 133... |
Line 146... |
input wb_we_i; // WISHBONE write enable input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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`ifdef WISHBONE_DMA
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// DMA
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// DMA
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input [1:0] wb_ack_i; // DMA acknowledge input
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output wb_rd_o; // DMA restart descriptor output
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output wb_rd_o; // DMA restart descriptor output
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`else
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// WISHBONE master
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output [31:0] m_wb_adr_o;
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output [3:0] m_wb_sel_o;
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output m_wb_we_o;
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input [31:0] m_wb_dat_i;
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output [31:0] m_wb_dat_o;
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output m_wb_cyc_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
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input m_wb_err_i;
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`endif
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input [1:0] wb_ack_i; // DMA acknowledge input
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// Tx
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// Tx
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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| Line 154... |
Line 181... |
input mrxerr_pad_i; // Receive data error (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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// Common Tx and Rx
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// Common Tx and Rx
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input mcoll_pad_i; // Collision (from PHY)
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input mcoll_pad_i; // Collision (from PHY)
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input mcrs_pad_i; // Carrier sense (from PHY)
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input mcrs_pad_i; // Carrier sense (from PHY)
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input RxAbort; // igor !!! Ta se mora preseliti da bo prisel iz enega izmed modulov. Tu je le zaradi
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// testiranja. Pove, kdaj adresa ni ustrezala in se paketi sklirajo, stevci pa resetirajo.
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// MII Management interface
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// MII Management interface
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input md_pad_i; // MII data input (from I/O cell)
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input md_pad_i; // MII data input (from I/O cell)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output md_pad_o; // MII data output (to I/O cell)
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output md_pad_o; // MII data output (to I/O cell)
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| Line 297... |
Line 326... |
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wire [7:0] RxData;
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wire [7:0] RxData;
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wire RxValid;
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wire RxValid;
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wire RxStartFrm;
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wire RxStartFrm;
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wire RxEndFrm;
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wire RxEndFrm;
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wire RxAbort;
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wire WillTransmit; // Will transmit (to RxEthMAC)
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wire WillTransmit; // Will transmit (to RxEthMAC)
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wire ResetCollision; // Reset Collision (for synchronizing collision)
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wire ResetCollision; // Reset Collision (for synchronizing collision)
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wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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wire WillSendControlFrame;
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wire WillSendControlFrame;
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| Line 493... |
Line 523... |
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// Connecting WishboneDMA module
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// Connecting WishboneDMA module
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eth_wishbonedma wbdma
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`ifdef WISHBONE_DMA
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eth_wishbonedma wishbone
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`else
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eth_wishbone wishbone
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`endif
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(
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(
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.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_DAT_O(DMA_WB_DAT_O),
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.WB_DAT_O(DMA_WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
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.WB_RD_O(wb_rd_o),
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.Reset(wb_rst_i),
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`ifdef WISHBONE_DMA
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.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
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.WB_ACK_I(wb_ack_i),
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`else
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// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
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.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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`endif
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//TX
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//TX
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.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
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.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
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.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
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.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
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.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
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.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
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| Line 522... |
Line 568... |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
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`ifdef WISHBONE_DMA
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`else
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,
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.RxAbort(RxAbort)
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`endif
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);
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);
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// Connecting MacStatus module
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// Connecting MacStatus module
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