| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/10/09 13:16:51 tadejm
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// Just back-up; not completed testbench and some testcases are not
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// wotking properly yet.
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//
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// Revision 1.5 2002/09/18 17:55:08 tadej
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// Revision 1.5 2002/09/18 17:55:08 tadej
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// Bug repaired in eth_phy device
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// Bug repaired in eth_phy device
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//
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//
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// Revision 1.3 2002/09/13 14:50:15 mohor
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// Revision 1.3 2002/09/13 14:50:15 mohor
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// Bug in MIIM fixed.
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// Bug in MIIM fixed.
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| Line 948... |
Line 952... |
reg tx_sfd_ok;
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reg tx_sfd_ok;
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// if there is a drible nibble, then tx packet is not byte aligned!
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// if there is a drible nibble, then tx packet is not byte aligned!
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reg tx_byte_aligned_ok;
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reg tx_byte_aligned_ok;
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// complete length of TX packet (Bytes) received (without preamble and SFD)
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// complete length of TX packet (Bytes) received (without preamble and SFD)
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reg [31:0] tx_len;
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reg [31:0] tx_len;
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// complete length of TX packet (Bytes) received (without preamble and SFD) untill MTxErr signal was set first
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reg [31:0] tx_len_err;
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// TX control
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// TX control
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always@(posedge mtx_clk_o)
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always@(posedge mtx_clk_o)
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begin
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begin
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// storing data and basic checking of frame
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// storing data and basic checking of frame
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| Line 959... |
Line 965... |
begin
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begin
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tx_cnt <= 0;
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tx_cnt <= 0;
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tx_preamble_ok <= 0;
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tx_preamble_ok <= 0;
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tx_sfd_ok <= 0;
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tx_sfd_ok <= 0;
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tx_len <= 0;
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tx_len <= 0;
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tx_len_err <= 0;
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end
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end
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else
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else
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begin
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begin
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if (!mtxen_i)
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if (!mtxen_i)
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begin
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begin
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| Line 983... |
Line 990... |
else
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else
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tx_preamble_ok <= 0;
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tx_preamble_ok <= 0;
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tx_sfd_ok <= 0;
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tx_sfd_ok <= 0;
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tx_byte_aligned_ok <= 0;
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tx_byte_aligned_ok <= 0;
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tx_len <= 0;
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tx_len <= 0;
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tx_len_err <= 0;
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// tx_mem_addr_in <= 0;
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// tx_mem_addr_in <= 0;
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end
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end
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// check preamble
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// check preamble
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if ((tx_cnt > 0) && (tx_cnt <= 13))
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if ((tx_cnt > 0) && (tx_cnt <= 13))
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| Line 1037... |
Line 1045... |
tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]}; // storing data into tx memory
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tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]}; // storing data into tx memory
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tx_len <= tx_len + 1; // enlarge byte length counter
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tx_len <= tx_len + 1; // enlarge byte length counter
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tx_byte_aligned_ok <= 1; // if transfer will stop after this, then transfer is byte alligned
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tx_byte_aligned_ok <= 1; // if transfer will stop after this, then transfer is byte alligned
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tx_mem_addr_in <= tx_mem_addr_in + 1'b1;
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tx_mem_addr_in <= tx_mem_addr_in + 1'b1;
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end
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end
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if (mtxerr_i)
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tx_len_err <= tx_len;
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end
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end
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end
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end
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end
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end
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// generating CARRIER SENSE for TX with or without delay
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// generating CARRIER SENSE for TX with or without delay
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