| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/02/06 14:11:35 mohor
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// non-DMA host interface added. Select the right configutation in eth_defines.
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//
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// Revision 1.6 2001/12/08 12:36:00 mohor
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// Revision 1.6 2001/12/08 12:36:00 mohor
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// TX_BD_NUM register added instead of the RB_BD_ADDR.
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// TX_BD_NUM register added instead of the RB_BD_ADDR.
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//
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//
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// Revision 1.5 2001/10/19 11:24:04 mohor
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// Revision 1.5 2001/10/19 11:24:04 mohor
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// Number of addresses (wb_adr_i) minimized.
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// Number of addresses (wb_adr_i) minimized.
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| Line 701... |
Line 704... |
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WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
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WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
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WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h00022043, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
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WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
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WishboneWrite(32'h12345678, {26'h0, `ETH_HASH0_ADR<<2});
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WishboneWrite(32'h98765432, {26'h0, `ETH_HASH1_ADR<<2});
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WishboneRead({26'h0, `ETH_HASH0_ADR<<2}); // Read from HASH0 register
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WishboneRead({26'h0, `ETH_HASH1_ADR<<2}); // Read from HASH1 register
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SendPacket(16'h0010, 1'b0);
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SendPacket(16'h0007, 1'b0);
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SendPacket(16'h0011, 1'b0);
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SendPacket(16'h0011, 1'b0);
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SendPacket(16'h0012, 1'b0);
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SendPacket(16'h0012, 1'b0);
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SendPacket(16'h0013, 1'b0);
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SendPacket(16'h0013, 1'b0);
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SendPacket(16'h0014, 1'b0);
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SendPacket(16'h0014, 1'b0);
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| Line 722... |
Line 730... |
SendPacket(16'h0045, 1'b0);
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SendPacket(16'h0045, 1'b0);
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SendPacket(16'h0025, 1'b0);
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SendPacket(16'h0025, 1'b0);
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SendPacket(16'h0017, 1'b0);
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SendPacket(16'h0017, 1'b0);
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// ReceivePacket(16'h0012, 1'b1, 1'b0); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
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// ReceivePacket(16'h0012, 1'b1, 1'b0); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
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ReceivePacket(16'h0015, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h000b, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0016, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0016, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
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repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
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| Line 750... |
Line 758... |
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
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#100000 $stop;
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#100000 $stop;
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end
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end
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//integer ijk;
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integer ijk;
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//initial
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initial
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//ijk = 0; // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
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ijk = 0; // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
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// Answering to master Wishbone requests
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// Answering to master Wishbone requests
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//wire [31:0] daatax = 32'h87654321;
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//wire [31:0] daatay = 32'h00edcba9;
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always @ (posedge WB_CLK_I)
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always @ (posedge WB_CLK_I)
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begin
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begin
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if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
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if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
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begin
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begin
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repeat(3) @ (posedge WB_CLK_I);
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repeat(3) @ (posedge WB_CLK_I);
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begin
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begin
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// if(ijk==41)
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if(ijk==6) // mama
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MColl = 1;
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// if(ijk==9)
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else
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MColl = 0;
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// begin
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// begin
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// repeat(1000) @ (posedge WB_CLK_I);
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// repeat(1000) @ (posedge WB_CLK_I);
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// end
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// end
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// else
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// else
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m_wb_ack_i <=#Tp 1'b1;
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m_wb_ack_i <=#Tp 1'b1;
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if(~m_wb_we_o)
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if(~m_wb_we_o)
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begin
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begin
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#Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
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#Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
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// #Tp m_wb_dat_i = ijk? daatay : daatax;
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$fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
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$fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
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// ijk = ijk + 1;
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end
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end
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else
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else
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$fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
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$fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
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end
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end
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@ (posedge WB_CLK_I);
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@ (posedge WB_CLK_I);
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ijk = ijk + 1;
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m_wb_ack_i <=#Tp 1'b0;
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m_wb_ack_i <=#Tp 1'b0;
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end
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end
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end
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end
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// Generating error
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// Generating error
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| Line 902... |
Line 918... |
TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
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TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
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TempData = 32'h78563411;
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TempData = 32'h78563411;
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WishboneWrite(TempData, TempAddr); // buffer pointer
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WishboneWrite(TempData, TempAddr); // buffer pointer
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TempAddr = {22'h01, (TxBDIndex<<2)}; // igor !!! zbrisi spodnjo vrstico
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TempAddr = {22'h01, (TxBDIndex<<2)};
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// TempAddr = {22'h01, 10'b1010010100};
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TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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#1;
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#1;
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// if(TxBDIndex == 6) // Only 4 buffer descriptors are used
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// if(TxBDIndex == 6) // Only 4 buffer descriptors are used
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| Line 969... |
Line 984... |
task GetDataOnMRxD;
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task GetDataOnMRxD;
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input [15:0] Len;
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input [15:0] Len;
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input abort;
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input abort;
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integer tt;
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integer tt;
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// reg [87:0] ddata;
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begin
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begin
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// ddata = 88'h50727196edcba987654321;
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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MRxDV=1'b1;
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MRxDV=1'b1;
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for(tt=0; tt<15; tt=tt+1)
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for(tt=0; tt<15; tt=tt+1)
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begin
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begin
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| Line 990... |
Line 1009... |
RxAbort<=#1 abort;
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RxAbort<=#1 abort;
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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MRxD=tt[7:4];
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MRxD=tt[7:4];
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RxAbort<=#1 0;
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RxAbort<=#1 0;
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end
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end
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/*
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for(tt=0; tt<Len; tt=tt+1)
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begin
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@ (posedge MRxClk);
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MRxD=ddata[3:0];
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$display("MRxD=0x%0x", MRxD);
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if(tt==9)
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RxAbort<=#1 abort;
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@ (posedge MRxClk);
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MRxD=ddata[7:4];
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$display("MRxD=0x%0x", MRxD);
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ddata[87:0] = {8'h0, ddata[87:8]};
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RxAbort<=#1 0;
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end
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*/
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@ (posedge MRxClk);
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@ (posedge MRxClk);
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MRxDV=1'b0;
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MRxDV=1'b0;
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end
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end
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endtask
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endtask
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