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https://opencores.org/ocsvn/ethmac/ethmac/trunk
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Rev 121 |
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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/07/19 14:02:47 mohor
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// Clock mrx_clk set to 2.5 MHz.
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//
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// Revision 1.1 2002/07/19 13:57:53 mohor
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// Revision 1.1 2002/07/19 13:57:53 mohor
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// Testing environment also includes traffic cop, memory interface and host
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// Testing environment also includes traffic cop, memory interface and host
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// interface.
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// interface.
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//
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//
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//
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//
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integer tx_log;
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integer tx_log;
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integer rx_log;
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integer rx_log;
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reg StartTB;
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reg StartTB;
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`ifdef ETH_XILINX_RAMB4
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reg gsr;
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`endif
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integer packet_ready_cnt, send_packet_cnt;
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integer packet_ready_cnt, send_packet_cnt;
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// Ethernet Slave Interface signals
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// Ethernet Slave Interface signals
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wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
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wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
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packet_ready_cnt = 0;
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packet_ready_cnt = 0;
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send_packet_cnt = 0;
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send_packet_cnt = 0;
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tx_log = $fopen("ethernet_tx.log");
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tx_log = $fopen("ethernet_tx.log");
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rx_log = $fopen("ethernet_rx.log");
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rx_log = $fopen("ethernet_rx.log");
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wb_rst_o = 1'b1;
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wb_rst_o = 1'b1;
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`ifdef ETH_XILINX_RAMB4
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gsr = 1'b0;
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#100 gsr = 1'b1;
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#100 gsr = 1'b0;
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`endif
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#100 wb_rst_o = 1'b0;
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#100 wb_rst_o = 1'b0;
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#100 StartTB = 1'b1;
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#100 StartTB = 1'b1;
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end
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end
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`ifdef ETH_XILINX_RAMB4
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assign glbl.GSR = gsr;
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`endif
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// Generating wb_clk_o clock
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// Generating wb_clk_o clock
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initial
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initial
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begin
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begin
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