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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 178 and 179

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Rev 178 Rev 179
Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.9  2002/09/13 18:41:45  mohor
 
// Rearanged testcases
 
//
// Revision 1.8  2002/09/13 14:50:15  mohor
// Revision 1.8  2002/09/13 14:50:15  mohor
// Bug in MIIM fixed.
// Bug in MIIM fixed.
//
//
// Revision 1.7  2002/09/13 12:29:14  mohor
// Revision 1.7  2002/09/13 12:29:14  mohor
// Headers changed.
// Headers changed.
Line 4252... Line 4255...
    if (wb_int !== 1'b0)
    if (wb_int !== 1'b0)
    begin
    begin
      test_fail("WB INT signal should not be set");
      test_fail("WB INT signal should not be set");
      fail = fail + 1;
      fail = fail + 1;
    end
    end
 
    // INTERMEDIATE DISPLAYS
 
    if (i_length == min_tmp - 4)
 
      tmp_data = min_tmp;
 
    if (i_length == (max_tmp - 4))
 
    begin
 
      $display("    packets with lengths (including FCS) from %d to %d are checked",
 
               tmp_data, (i_length + 4));
 
    end
 
    else if (i_length[7:0] == 8'h7C) // 8'h7C + 8'h04 = 8'h80 (128), because i_length has length - 4 value
 
    begin
 
      $display("    packets with lengths (including FCS) from %d to %d are checked",
 
               tmp_data, (i_length + 4));
 
      tmp_data = i_length + 4 + 1; // next starting length is for +1 longer
 
    end
  end
  end
  // disable TX
  // disable TX
  wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
  wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
  if(fail == 0)
  if(fail == 0)

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