| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.11 2002/09/13 19:18:04 mohor
|
|
// Bench outputs data to display every 128 bytes.
|
|
//
|
// Revision 1.10 2002/09/13 18:44:29 mohor
|
// Revision 1.10 2002/09/13 18:44:29 mohor
|
// Beautiful tests merget together
|
// Beautiful tests merget together
|
//
|
//
|
// Revision 1.9 2002/09/13 18:41:45 mohor
|
// Revision 1.9 2002/09/13 18:41:45 mohor
|
// Rearanged testcases
|
// Rearanged testcases
|
| Line 393... |
Line 396... |
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
|
// Call tests
|
// Call tests
|
// ----------
|
// ----------
|
// test_access_to_mac_reg(0, 3); // 0 - 3
|
test_access_to_mac_reg(0, 3); // 0 - 3
|
// test_mii(0, 17); // 0 - 17
|
test_mii(0, 17); // 0 - 17
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
test_mac_full_duplex_transmit(0, 3); // 0 - (3)
|
test_mac_full_duplex_transmit(0, 3); // 0 - (3)
|
|
|
test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
|
test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
|
| Line 473... |
Line 476... |
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
begin
|
begin
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 0: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 0: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
begin
|
begin
|
wbm_init_waits = i;
|
wbm_init_waits = i;
|
| Line 681... |
Line 684... |
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
|
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
|
begin
|
begin
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
test_name = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 1: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 1: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
// set TX and RX buffer descriptors
|
// set TX and RX buffer descriptors
|
tx_bd_num = 32'h40;
|
tx_bd_num = 32'h40;
|
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
|
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
|
| Line 797... |
Line 800... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) // Start this task
|
if (test_num == 2) // Start this task
|
begin
|
begin
|
// TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
// TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
test_name =
|
test_name =
|
"TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
"TEST 2: TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
`TIME; $display(
|
`TIME; $display(
|
" TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
|
" TEST 2: TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
|
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
|
begin
|
begin
|
| Line 995... |
Line 998... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test buffer desc. ram preserving values after hard reset ////
|
|
//// of the mac and reseting the logic ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) // Start this task
|
if (test_num == 3) // Start this task
|
begin
|
begin
|
// TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
// TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
test_name = "TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
test_name = "TEST 3: TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
`TIME;
|
`TIME;
|
$display(" TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
$display(" TEST 3: TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset LOGIC with soft reset
|
// reset LOGIC with soft reset
|
reset_mac;
|
reset_mac;
|
| Line 1056... |
Line 1065... |
|
|
|
|
if (test_num == 4) // Start this task
|
if (test_num == 4) // Start this task
|
begin
|
begin
|
/* // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
/* // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 4: TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 4: TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
burst_data = 0;
|
burst_data = 0;
|
burst_tmp_data = 0;
|
burst_tmp_data = 0;
|
i_length = 10; // two bursts for length 20
|
i_length = 10; // two bursts for length 20
|
| Line 1315... |
Line 1324... |
integer i1;
|
integer i1;
|
integer i2;
|
integer i2;
|
integer i3;
|
integer i3;
|
integer cnt;
|
integer cnt;
|
integer fail;
|
integer fail;
|
|
integer test_num;
|
reg [8:0] clk_div; // only 8 bits are valid!
|
reg [8:0] clk_div; // only 8 bits are valid!
|
reg [4:0] phy_addr;
|
reg [4:0] phy_addr;
|
reg [4:0] reg_addr;
|
reg [4:0] reg_addr;
|
reg [15:0] phy_data;
|
reg [15:0] phy_data;
|
reg [15:0] tmp_data;
|
reg [15:0] tmp_data;
|
| Line 1330... |
Line 1340... |
fail = 0;
|
fail = 0;
|
|
|
// reset MIIM LOGIC with soft reset
|
// reset MIIM LOGIC with soft reset
|
reset_mii;
|
reset_mii;
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
if ((start_task <= 0) && (end_task >= 0))
|
//// ////
|
|
//// test_mii: ////
|
|
//// ////
|
|
//// 0: Test clock divider of mii management module with all ////
|
|
//// possible frequences. ////
|
|
//// 1: Test various readings from 'real' phy registers. ////
|
|
//// 2: Test various writings to 'real' phy registers (control ////
|
|
//// and non writable registers) ////
|
|
//// 3: Test reset phy through mii management module ////
|
|
//// 4: Test 'walking one' across phy address (with and without ////
|
|
//// preamble) ////
|
|
//// 5: Test 'walking one' across phy's register address (with ////
|
|
//// and without preamble) ////
|
|
//// 6: Test 'walking one' across phy's data (with and without ////
|
|
//// preamble) ////
|
|
//// 7: Test reading from phy with wrong phy address (host ////
|
|
//// reading high 'z' data) ////
|
|
//// 8: Test writing to phy with wrong phy address and reading ////
|
|
//// from correct one ////
|
|
//// 9: Test sliding stop scan command immediately after read ////
|
|
//// request (with and without preamble) ////
|
|
//// 10: Test sliding stop scan command immediately after write ////
|
|
//// request (with and without preamble) ////
|
|
//// 11: Test busy and nvalid status durations during write ////
|
|
//// (with and without preamble) ////
|
|
//// 12: Test busy and nvalid status durations during write ////
|
|
//// (with and without preamble) ////
|
|
//// 13: Test busy and nvalid status durations during scan (with ////
|
|
//// and without preamble) ////
|
|
//// 14: Test scan status from phy with detecting link-fail bit ////
|
|
//// (with and without preamble) ////
|
|
//// 15: Test scan status from phy with sliding link-fail bit ////
|
|
//// (with and without preamble) ////
|
|
//// 16: Test sliding stop scan command immediately after scan ////
|
|
//// request (with and without preamble) ////
|
|
//// 17: Test sliding stop scan command after 2. scan (with and ////
|
|
//// without preamble) ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
begin
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test clock divider of mii management module with all ////
|
|
//// possible frequences. ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
|
begin
|
begin
|
// TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
|
// TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
|
test_name = "TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
|
test_name = "TEST 0: TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
|
`TIME; $display(" TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
|
`TIME; $display(" TEST 0: TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
|
|
|
wait(Mdc_O); // wait for MII clock to be 1
|
wait(Mdc_O); // wait for MII clock to be 1
|
for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
|
for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
|
begin
|
begin
|
i1 = 0;
|
i1 = 0;
|
| Line 1399... |
Line 1456... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 1) && (end_task >= 1))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test various readings from 'real' phy registers. ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) // Test various readings from 'real' phy registers.
|
begin
|
begin
|
// TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS
|
// TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS
|
test_name = "TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
|
test_name = "TEST 1: TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
|
`TIME; $display(" TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
|
`TIME; $display(" TEST 1: TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
|
|
|
// set the fastest possible MII
|
// set the fastest possible MII
|
clk_div = 0;
|
clk_div = 0;
|
mii_set_clk_div(clk_div[7:0]);
|
mii_set_clk_div(clk_div[7:0]);
|
// set address
|
// set address
|
| Line 1448... |
Line 1510... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 2) && (end_task >= 2))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test various writings to 'real' phy registers (control ////
|
|
//// and non writable registers) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
|
// TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
|
test_name = "TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
|
test_name = "TEST 2: TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
|
`TIME; $display(" TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
|
`TIME; $display(" TEST 2: TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
|
|
|
// negate data and try to write into unwritable register
|
// negate data and try to write into unwritable register
|
tmp_data = ~phy_data;
|
tmp_data = ~phy_data;
|
// write request
|
// write request
|
#Tp mii_write_req(phy_addr, reg_addr, tmp_data);
|
#Tp mii_write_req(phy_addr, reg_addr, tmp_data);
|
| Line 1511... |
Line 1579... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 3) && (end_task >= 3))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test reset phy through mii management module ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST RESET PHY THROUGH MII MANAGEMENT MODULE
|
// TEST RESET PHY THROUGH MII MANAGEMENT MODULE
|
test_name = "TEST RESET PHY THROUGH MII MANAGEMENT MODULE";
|
test_name = "TEST 3: TEST RESET PHY THROUGH MII MANAGEMENT MODULE";
|
`TIME; $display(" TEST RESET PHY THROUGH MII MANAGEMENT MODULE");
|
`TIME; $display(" TEST 3: TEST RESET PHY THROUGH MII MANAGEMENT MODULE");
|
|
|
// set address
|
// set address
|
reg_addr = 5'h0; // control register
|
reg_addr = 5'h0; // control register
|
// write request
|
// write request
|
phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
|
phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
|
| Line 1562... |
Line 1635... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 4) && (end_task >= 4))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test 'walking one' across phy address (with and without ////
|
|
//// preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 4) //
|
begin
|
begin
|
// TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
// TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 4: TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 4: TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set PHY to test mode
|
// set PHY to test mode
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
for (i = 0; i <= 1; i = i + 1)
|
for (i = 0; i <= 1; i = i + 1)
|
begin
|
begin
|
| Line 1615... |
Line 1694... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 5) && (end_task >= 5))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test 'walking one' across phy's register address (with ////
|
|
//// and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
// TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 5: TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 5: TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set PHY to test mode
|
// set PHY to test mode
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
for (i = 0; i <= 1; i = i + 1)
|
for (i = 0; i <= 1; i = i + 1)
|
begin
|
begin
|
| Line 1668... |
Line 1753... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 6) && (end_task >= 6))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test 'walking one' across phy's data (with and without ////
|
|
//// preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 6) //
|
begin
|
begin
|
// TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
|
// TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 6: TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 6: TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set PHY to test mode
|
// set PHY to test mode
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
for (i = 0; i <= 1; i = i + 1)
|
for (i = 0; i <= 1; i = i + 1)
|
begin
|
begin
|
| Line 1721... |
Line 1812... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 7) && (end_task >= 7))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test reading from phy with wrong phy address (host ////
|
|
//// reading high 'z' data) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 7) //
|
begin
|
begin
|
// TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
|
// TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
|
test_name = "TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
|
test_name = "TEST 7: TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
|
`TIME; $display(" TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
|
`TIME; $display(" TEST 7: TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
|
|
|
phy_addr = 5'h2; // wrong PHY address
|
phy_addr = 5'h2; // wrong PHY address
|
// read request
|
// read request
|
#Tp mii_read_req(phy_addr, reg_addr);
|
#Tp mii_read_req(phy_addr, reg_addr);
|
check_mii_busy; // wait for read to finish
|
check_mii_busy; // wait for read to finish
|
| Line 1746... |
Line 1843... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 8) && (end_task >= 8))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test writing to phy with wrong phy address and reading ////
|
|
//// from correct one ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 8) //
|
begin
|
begin
|
// TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
|
// TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
|
test_name = "TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
|
test_name = "TEST 8: TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
|
`TIME; $display(" TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
|
`TIME; $display(" TEST 8: TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
|
|
|
// set address
|
// set address
|
reg_addr = 5'h0; // control register
|
reg_addr = 5'h0; // control register
|
phy_addr = 5'h2; // wrong PHY address
|
phy_addr = 5'h2; // wrong PHY address
|
// write request
|
// write request
|
| Line 1778... |
Line 1881... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 9) && (end_task >= 9))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test sliding stop scan command immediately after read ////
|
|
//// request (with and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 9) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 9: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
`TIME;
|
`TIME;
|
$display(" TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
$display(" TEST 9: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 1951... |
Line 2060... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 10) && (end_task >= 10))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test sliding stop scan command immediately after write ////
|
|
//// request (with and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 10) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 10: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
`TIME;
|
`TIME;
|
$display(" TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
$display(" TEST 10: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 2125... |
Line 2240... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 11) && (end_task >= 11))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test busy and nvalid status durations during write (with ////
|
|
//// and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 11) //
|
begin
|
begin
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 11: TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 11: TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
| Line 2317... |
Line 2438... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 12) && (end_task >= 12))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test busy and nvalid status durations during write (with ////
|
|
//// and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 12) //
|
begin
|
begin
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 12: TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 12: TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
| Line 2511... |
Line 2638... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 13) && (end_task >= 13))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test busy and nvalid status durations during scan (with ////
|
|
//// and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 13) //
|
begin
|
begin
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 13: TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 13: TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
| Line 2753... |
Line 2886... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 14) && (end_task >= 14))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test scan status from phy with detecting link-fail bit ////
|
|
//// (with and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 14) //
|
begin
|
begin
|
// TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
// TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 14: TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 14: TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set MII speed
|
// set MII speed
|
| Line 2998... |
Line 3137... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 15) && (end_task >= 15))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test scan status from phy with sliding link-fail bit ////
|
|
//// (with and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 15) //
|
begin
|
begin
|
// TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
// TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 15: TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 15: TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set address
|
// set address
|
reg_addr = 5'h1; // status register
|
reg_addr = 5'h1; // status register
|
phy_addr = 5'h1; // correct PHY address
|
phy_addr = 5'h1; // correct PHY address
|
|
|
| Line 3372... |
Line 3517... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 16) && (end_task >= 16))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test sliding stop scan command immediately after scan ////
|
|
//// request (with and without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 16) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 16: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
`TIME;
|
`TIME;
|
$display(" TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
$display(" TEST 16: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 3573... |
Line 3724... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 17) && (end_task >= 17))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test sliding stop scan command after 2. scan (with and ////
|
|
//// without preamble) ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 17) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
|
// TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 17: TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 17: TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 3831... |
Line 3988... |
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
end
|
end
|
endtask // test_mii
|
endtask // test_mii
|
|
|
|
|
task test_mac_full_duplex_transmit;
|
task test_mac_full_duplex_transmit;
|
