| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.14 2002/09/18 17:56:38 tadej
|
|
// Some additional reports added
|
|
//
|
// Revision 1.13 2002/09/16 17:53:49 tadej
|
// Revision 1.13 2002/09/16 17:53:49 tadej
|
// Full duplex test improved.
|
// Full duplex test improved.
|
//
|
//
|
// Revision 1.12 2002/09/16 15:10:42 mohor
|
// Revision 1.12 2002/09/16 15:10:42 mohor
|
// MIIM test look better.
|
// MIIM test look better.
|
| Line 402... |
Line 405... |
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
|
// Call tests
|
// Call tests
|
// ----------
|
// ----------
|
test_access_to_mac_reg(0, 3); // 0 - 3
|
// test_access_to_mac_reg(0, 3); // 0 - 3
|
test_mii(0, 17); // 0 - 17
|
// test_mii(0, 17); // 0 - 17
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
test_mac_full_duplex_transmit(0, 3); // 0 - (3)
|
test_mac_full_duplex_transmit(2, 3); // 0 - (3)
|
|
|
test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
|
test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(1);
|
eth_phy.carrier_sense_real_delay(1);
|
|
|
|
|
| Line 487... |
Line 490... |
//// Walking 1 with single cycles across MAC regs. ////
|
//// Walking 1 with single cycles across MAC regs. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
begin
|
begin
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
// TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 0: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 0: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
begin
|
begin
|
wbm_init_waits = i;
|
wbm_init_waits = i;
|
| Line 679... |
Line 682... |
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
$display(" buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0; // Errors were reported previously
|
fail = 0; // Errors were reported previously
|
end
|
end
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
|
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
|
begin
|
begin
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
test_name = "TEST 1: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 1: TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
// set TX and RX buffer descriptors
|
// set TX and RX buffer descriptors
|
tx_bd_num = 32'h40;
|
tx_bd_num = 32'h40;
|
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
|
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
|
| Line 810... |
Line 812... |
//// inverse reset values and hard reset of the MAC ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) // Start this task
|
if (test_num == 2) // Start this task
|
begin
|
begin
|
// TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
// TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
test_name =
|
test_name =
|
"TEST 2: TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
"TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
`TIME; $display(
|
`TIME; $display(
|
" TEST 2: TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
|
" TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
|
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
|
begin
|
begin
|
| Line 1018... |
Line 1020... |
//// of the mac and reseting the logic ////
|
//// of the mac and reseting the logic ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) // Start this task
|
if (test_num == 3) // Start this task
|
begin
|
begin
|
// TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
// TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
test_name = "TEST 3: TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
test_name = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
`TIME;
|
`TIME;
|
$display(" TEST 3: TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
$display(" TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset LOGIC with soft reset
|
// reset LOGIC with soft reset
|
reset_mac;
|
reset_mac;
|
| Line 1076... |
Line 1078... |
end
|
end
|
|
|
|
|
if (test_num == 4) // Start this task
|
if (test_num == 4) // Start this task
|
begin
|
begin
|
/* // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
/* // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 4: TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 4: TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
burst_data = 0;
|
burst_data = 0;
|
burst_tmp_data = 0;
|
burst_tmp_data = 0;
|
i_length = 10; // two bursts for length 20
|
i_length = 10; // two bursts for length 20
|
| Line 1355... |
Line 1357... |
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
// reset MAC and MII LOGIC with soft reset
|
reset_mac;
|
reset_mac;
|
reset_mii;
|
reset_mii;
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// test_mii: ////
|
//// test_mii: ////
|
//// ////
|
//// ////
|
//// 0: Test clock divider of mii management module with all ////
|
//// 0: Test clock divider of mii management module with all ////
|
| Line 1397... |
Line 1400... |
//// without preamble) ////
|
//// without preamble) ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
begin
|
begin
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test clock divider of mii management module with all ////
|
//// Test clock divider of mii management module with all ////
|
//// possible frequences. ////
|
//// possible frequences. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
|
if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
|
begin
|
begin
|
// TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
|
// TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
|
test_name = "TEST 0: TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
|
test_name = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
|
`TIME; $display(" TEST 0: TEST CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
|
`TIME; $display(" TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
|
|
|
wait(Mdc_O); // wait for MII clock to be 1
|
wait(Mdc_O); // wait for MII clock to be 1
|
for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
|
for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
|
begin
|
begin
|
i1 = 0;
|
i1 = 0;
|
| Line 1478... |
Line 1482... |
//// Test various readings from 'real' phy registers. ////
|
//// Test various readings from 'real' phy registers. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Test various readings from 'real' phy registers.
|
if (test_num == 1) // Test various readings from 'real' phy registers.
|
begin
|
begin
|
// TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS
|
// TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
|
test_name = "TEST 1: TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
|
test_name = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
|
`TIME; $display(" TEST 1: TEST VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
|
`TIME; $display(" TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
|
|
|
// set the fastest possible MII
|
// set the fastest possible MII
|
clk_div = 0;
|
clk_div = 0;
|
mii_set_clk_div(clk_div[7:0]);
|
mii_set_clk_div(clk_div[7:0]);
|
// set address
|
// set address
|
| Line 1533... |
Line 1537... |
//// and non writable registers) ////
|
//// and non writable registers) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) //
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
|
// TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
|
test_name = "TEST 2: TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
|
test_name = "TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
|
`TIME; $display(" TEST 2: TEST VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
|
`TIME; $display(" TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
|
|
|
// negate data and try to write into unwritable register
|
// negate data and try to write into unwritable register
|
tmp_data = ~phy_data;
|
tmp_data = ~phy_data;
|
// write request
|
// write request
|
#Tp mii_write_req(phy_addr, reg_addr, tmp_data);
|
#Tp mii_write_req(phy_addr, reg_addr, tmp_data);
|
| Line 1601... |
Line 1605... |
//// Test reset phy through mii management module ////
|
//// Test reset phy through mii management module ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) //
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST RESET PHY THROUGH MII MANAGEMENT MODULE
|
// TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE
|
test_name = "TEST 3: TEST RESET PHY THROUGH MII MANAGEMENT MODULE";
|
test_name = "TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE";
|
`TIME; $display(" TEST 3: TEST RESET PHY THROUGH MII MANAGEMENT MODULE");
|
`TIME; $display(" TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE");
|
|
|
// set address
|
// set address
|
reg_addr = 5'h0; // control register
|
reg_addr = 5'h0; // control register
|
// write request
|
// write request
|
phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
|
phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
|
| Line 1658... |
Line 1662... |
//// preamble) ////
|
//// preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 4) //
|
if (test_num == 4) //
|
begin
|
begin
|
// TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
// TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 4: TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 4: TEST 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set PHY to test mode
|
// set PHY to test mode
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
for (i = 0; i <= 1; i = i + 1)
|
for (i = 0; i <= 1; i = i + 1)
|
begin
|
begin
|
| Line 1717... |
Line 1721... |
//// and without preamble) ////
|
//// and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 5) //
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
// TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 5: TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 5: TEST 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set PHY to test mode
|
// set PHY to test mode
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
for (i = 0; i <= 1; i = i + 1)
|
for (i = 0; i <= 1; i = i + 1)
|
begin
|
begin
|
| Line 1776... |
Line 1780... |
//// preamble) ////
|
//// preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 6) //
|
if (test_num == 6) //
|
begin
|
begin
|
// TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
|
// TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 6: TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 6: TEST 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set PHY to test mode
|
// set PHY to test mode
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
#Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
|
for (i = 0; i <= 1; i = i + 1)
|
for (i = 0; i <= 1; i = i + 1)
|
begin
|
begin
|
| Line 1835... |
Line 1839... |
//// reading high 'z' data) ////
|
//// reading high 'z' data) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 7) //
|
if (test_num == 7) //
|
begin
|
begin
|
// TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
|
// TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
|
test_name = "TEST 7: TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
|
test_name = "TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
|
`TIME; $display(" TEST 7: TEST READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
|
`TIME; $display(" TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
|
|
|
phy_addr = 5'h2; // wrong PHY address
|
phy_addr = 5'h2; // wrong PHY address
|
// read request
|
// read request
|
#Tp mii_read_req(phy_addr, reg_addr);
|
#Tp mii_read_req(phy_addr, reg_addr);
|
check_mii_busy; // wait for read to finish
|
check_mii_busy; // wait for read to finish
|
| Line 1866... |
Line 1870... |
//// from correct one ////
|
//// from correct one ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 8) //
|
if (test_num == 8) //
|
begin
|
begin
|
// TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
|
// TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
|
test_name = "TEST 8: TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
|
test_name = "TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
|
`TIME; $display(" TEST 8: TEST WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
|
`TIME; $display(" TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
|
|
|
// set address
|
// set address
|
reg_addr = 5'h0; // control register
|
reg_addr = 5'h0; // control register
|
phy_addr = 5'h2; // wrong PHY address
|
phy_addr = 5'h2; // wrong PHY address
|
// write request
|
// write request
|
| Line 1904... |
Line 1908... |
//// request (with and without preamble) ////
|
//// request (with and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 9) //
|
if (test_num == 9) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
|
// TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 9: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
`TIME;
|
`TIME;
|
$display(" TEST 9: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
$display(" TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 2083... |
Line 2087... |
//// request (with and without preamble) ////
|
//// request (with and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 10) //
|
if (test_num == 10) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
|
// TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 10: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
`TIME;
|
`TIME;
|
$display(" TEST 10: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
$display(" TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 2263... |
Line 2267... |
//// and without preamble) ////
|
//// and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 11) //
|
if (test_num == 11) //
|
begin
|
begin
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
|
// TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 11: TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 11: TEST BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
| Line 2461... |
Line 2465... |
//// and without preamble) ////
|
//// and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 12) //
|
if (test_num == 12) //
|
begin
|
begin
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
|
// TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 12: TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 12: TEST BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
| Line 2661... |
Line 2665... |
//// and without preamble) ////
|
//// and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 13) //
|
if (test_num == 13) //
|
begin
|
begin
|
// TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
|
// TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 13: TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 13: TEST BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
| Line 2909... |
Line 2913... |
//// (with and without preamble) ////
|
//// (with and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 14) //
|
if (test_num == 14) //
|
begin
|
begin
|
// TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
// TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 14: TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 14: TEST SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
reset_mii; // reset MII
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set MII speed
|
// set MII speed
|
| Line 3160... |
Line 3164... |
//// (with and without preamble) ////
|
//// (with and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 15) //
|
if (test_num == 15) //
|
begin
|
begin
|
// TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
// TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 15: TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 15: TEST SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
|
|
// set address
|
// set address
|
reg_addr = 5'h1; // status register
|
reg_addr = 5'h1; // status register
|
phy_addr = 5'h1; // correct PHY address
|
phy_addr = 5'h1; // correct PHY address
|
|
|
| Line 3540... |
Line 3544... |
//// request (with and without preamble) ////
|
//// request (with and without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 16) //
|
if (test_num == 16) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
|
// TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 16: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
|
`TIME;
|
`TIME;
|
$display(" TEST 16: TEST SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
$display(" TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 3747... |
Line 3751... |
//// without preamble) ////
|
//// without preamble) ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 17) //
|
if (test_num == 17) //
|
begin
|
begin
|
// TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
|
// TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 17: TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 17: TEST SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
|
|
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
|
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
| Line 4021... |
Line 4025... |
integer num_of_reg;
|
integer num_of_reg;
|
integer i_addr;
|
integer i_addr;
|
integer i_data;
|
integer i_data;
|
integer i_length;
|
integer i_length;
|
integer tmp_data;
|
integer tmp_data;
|
|
integer test_num;
|
reg [31:0] tx_bd_num;
|
reg [31:0] tx_bd_num;
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
integer i;
|
integer i;
|
integer i1;
|
integer i1;
|
| Line 4105... |
Line 4110... |
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
append_rx_crc
|
append_rx_crc
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
*/
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// test_mac_full_duplex_transmit: ////
|
|
//// ////
|
|
//// 0: Test no transmit when all buffers are RX ( 10Mbps ). ////
|
|
//// 1: Test no transmit when all buffers are RX ( 100Mbps ). ////
|
|
//// 2: Test transmit packets form MINFL to MAXFL sizes at ////
|
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
|
//// 3: Test transmit packets form MINFL to MAXFL sizes at ////
|
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
|
begin
|
|
|
if ((start_task <= 0) && (end_task >= 0))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test no transmit when all buffers are RX ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 0) // Test no transmit when all buffers are RX ( 10Mbps ).
|
begin
|
begin
|
// TEST NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
|
// TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
|
test_name = "TEST NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
|
test_name = "TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
|
`TIME; $display(" TEST NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
|
`TIME; $display(" TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
|
|
|
// unmask interrupts
|
// unmask interrupts
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXF | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXF | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set all buffer descriptors to RX - must be set before TX enable
|
// set all buffer descriptors to RX - must be set before TX enable
|
| Line 4189... |
Line 4213... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 1) && (end_task >= 1))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test no transmit when all buffers are RX ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) // Test no transmit when all buffers are RX ( 100Mbps ).
|
begin
|
begin
|
// TEST NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
|
// TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
|
test_name = "TEST NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
|
test_name = "TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
|
`TIME; $display(" TEST NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
|
`TIME; $display(" TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
|
|
|
// unmask interrupts
|
// unmask interrupts
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXF | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXF | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set all buffer descriptors to RX - must be set before TX enable
|
// set all buffer descriptors to RX - must be set before TX enable
|
| Line 4272... |
Line 4301... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 2) && (end_task >= 2))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
|
// TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
|
test_name = "TEST TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
|
test_name = "TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
|
`TIME; $display(" TEST TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
// // unmask interrupts
|
|
// wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXF | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
// `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set one TX buffer descriptor - must be set before TX enable
|
// set one TX buffer descriptor - must be set before TX enable
|
wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX, set full-duplex mode, padding and CRC appending
|
// enable TX, set full-duplex mode, padding and CRC appending
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 4308... |
Line 4340... |
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 10;
|
|
|
for (i_length = (min_tmp - 4); i_length <= (max_tmp - 4); i_length = i_length + 1)
|
i_length = (min_tmp - 4);
|
|
while (i_length <= (max_tmp - 4))
|
begin
|
begin
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
case (i_length[1:0])
|
case (i_length[1:0])
|
2'h0: // Interrupt is generated
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
| Line 4387... |
Line 4420... |
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
|
#1 check_tx_bd(0, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
repeat (2) @(posedge mtx_clk);
|
while (data[15] === 1)
|
repeat (3) @(posedge wb_clk);
|
begin
|
|
#1 check_tx_bd(0, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
// check length of a PACKET
|
// check length of a PACKET
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
| Line 4465... |
Line 4508... |
end
|
end
|
// clear TX buffer descriptor
|
// clear TX buffer descriptor
|
clear_tx_bd(0, 0);
|
clear_tx_bd(0, 0);
|
// check interrupts
|
// check interrupts
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (i_length[1:0] == 2'h0)
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
begin
|
begin
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Transmit Buffer was not set");
|
test_fail("Interrupt Transmit Buffer was not set");
|
| Line 4498... |
Line 4541... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (i_length == min_tmp - 4)
|
if ((i_length + 4) == (min_tmp + 64))
|
tmp_data = min_tmp;
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
if (i_length == (max_tmp - 4))
|
$display(" packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
begin
|
min_tmp, (min_tmp + 64));
|
$display(" packets with lengths from %0d to %0d (MAXFL) are checked (also packet data and CRC)",
|
else if ((i_length + 4) == (max_tmp - 16))
|
tmp_data, (i_length + 4));
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
end
|
$display(" packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
else if ( ((i_length + 4) !== 64) && (!((i_length + 4) % 64)) ) // display every 64 bytes, except for first byte
|
(min_tmp + 64 + 128), tmp_data);
|
begin
|
else if ((i_length + 4) == max_tmp)
|
if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
|
$display(" packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
$display(" packets with lengths from %0d to %0d are checked (also packet data and CRC)",
|
(max_tmp - (4 + 16)), max_tmp);
|
tmp_data, (i_length + 4));
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 64))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
begin
|
|
i_length = i_length + 128;
|
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
|
end
|
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
|
i_length = i_length + 1;
|
else
|
else
|
$display(" packets with lengths from %0d to %0d are checked",
|
begin
|
tmp_data, (i_length + 4));
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
tmp_data = i_length + 4 + 1; // next starting length is for +1 longer
|
#10 $stop;
|
end
|
end
|
end
|
end
|
// disable TX
|
// disable TX
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 4526... |
Line 4580... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 3) && (end_task >= 3))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
|
// TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
|
test_name = "TEST TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
|
test_name = "TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
|
`TIME; $display(" TEST TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
|
`TIME; $display(" TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
// // unmask interrupts
|
|
// wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXF | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
// `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set one TX buffer descriptor - must be set before TX enable
|
// set one TX buffer descriptor - must be set before TX enable
|
wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX, set full-duplex mode, padding and CRC appending
|
// enable TX, set full-duplex mode, padding and CRC appending
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 4562... |
Line 4619... |
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 100;
|
|
|
for (i_length = (min_tmp - 4); i_length <= (max_tmp - 4); i_length = i_length + 1)
|
i_length = (min_tmp - 4);
|
|
while (i_length <= (max_tmp - 4))
|
begin
|
begin
|
// choose generating carrier sense and collision
|
// choose generating carrier sense and collision
|
case (i_length[1:0])
|
case (i_length[1:0])
|
2'h0: // Interrupt is generated
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
| Line 4641... |
Line 4699... |
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
|
#1 check_tx_bd(0, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
repeat (2) @(posedge mtx_clk);
|
while (data[15] === 1)
|
repeat (3) @(posedge wb_clk);
|
begin
|
|
#1 check_tx_bd(0, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
// check length of a PACKET
|
// check length of a PACKET
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking in the following if statement is performed only for first and last 64 lengths
|
|
if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
|
|
begin
|
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
begin
|
begin
|
check_tx_packet(`MEMORY_BASE, max_tmp, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, max_tmp, i_length, tmp);
|
end
|
end
|
| Line 4675... |
Line 4740... |
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
|
// check WB INT signal
|
// check WB INT signal
|
if (i_length[1:0] == 2'h0)
|
if (i_length[1:0] == 2'h0)
|
begin
|
begin
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
| Line 4719... |
Line 4783... |
end
|
end
|
// clear TX buffer descriptor
|
// clear TX buffer descriptor
|
clear_tx_bd(0, 0);
|
clear_tx_bd(0, 0);
|
// check interrupts
|
// check interrupts
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (i_length[1:0] == 2'h0)
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
begin
|
begin
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Transmit Buffer was not set");
|
test_fail("Interrupt Transmit Buffer was not set");
|
| Line 4752... |
Line 4816... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (i_length == min_tmp - 4)
|
if ((i_length + 4) == (min_tmp + 64))
|
tmp_data = min_tmp;
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
if (i_length == (max_tmp - 4))
|
$display(" packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
begin
|
min_tmp, (min_tmp + 64));
|
$display(" packets with lengths from %0d to %0d (MAXFL) are checked (also packet data and CRC)",
|
else if ((i_length + 4) == (max_tmp - 16))
|
tmp_data, (i_length + 4));
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
end
|
$display(" packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
else if ( ((i_length + 4) !== 64) && (!((i_length + 4) % 64)) ) // display every 64 bytes, except for first byte
|
(min_tmp + 64 + 128), tmp_data);
|
begin
|
else if ((i_length + 4) == max_tmp)
|
if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
|
$display(" packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
$display(" packets with lengths from %0d to %0d are checked (also packet data and CRC)",
|
(max_tmp - (4 + 16)), max_tmp);
|
tmp_data, (i_length + 4));
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 64))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
begin
|
|
i_length = i_length + 128;
|
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
|
end
|
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
|
i_length = i_length + 1;
|
else
|
else
|
$display(" packets with lengths from %0d to %0d are checked",
|
begin
|
tmp_data, (i_length + 4));
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
tmp_data = i_length + 4 + 1; // next starting length is for +1 longer
|
#10 $stop;
|
end
|
end
|
end
|
end
|
// disable TX
|
// disable TX
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 4813... |
Line 4888... |
|
|
eth_phy.GetDataOnMRxD(70, `MULTICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
eth_phy.GetDataOnMRxD(70, `MULTICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
repeat (10000) @(posedge wb_clk); // Waiting for TxEthMac to finish transmit
|
repeat (10000) @(posedge wb_clk); // Waiting for TxEthMac to finish transmit
|
*/
|
*/
|
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
end
|
end
|
endtask // test_mac_full_duplex_transmit
|
endtask // test_mac_full_duplex_transmit
|
|
|
|
|
