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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [wb_model_defines.v] - Diff between revs 169 and 170

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//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  File name "wb_model_defines.v"                              ////
 
////                                                              ////
 
////  This file is part of the Ethernet IP core project           ////
 
////  http://www.opencores.org/projects/ethmac/                   ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Miha Dolenc (mihad@opencores.org)                     ////
 
////                                                              ////
 
////  All additional information is available in the README.pdf   ////
 
////  file.                                                       ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2002 Authors                                   ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//
 
// CVS Revision History
 
//
 
// $Log: not supported by cvs2svn $
 
//
 
//
 
//
 
 
// WISHBONE frequency in GHz
// WISHBONE frequency in GHz
`define WB_FREQ 0.100
`define WB_FREQ 0.100
 
 
// memory frequency in GHz
// memory frequency in GHz
`define MEM_FREQ 0.100
`define MEM_FREQ 0.100

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