| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2002/08/16 22:09:47 mohor
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// Defines for register width added. mii_rst signal in MIIMODER register
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// changed.
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//
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// Revision 1.20 2002/08/14 19:31:48 mohor
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// Revision 1.20 2002/08/14 19:31:48 mohor
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// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
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// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
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// need to multiply or devide any more.
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// need to multiply or devide any more.
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//
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//
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// Revision 1.19 2002/07/23 15:28:31 mohor
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// Revision 1.19 2002/07/23 15:28:31 mohor
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| Line 155... |
Line 159... |
`define ETH_MIISTATUS_ADR 8'hF // 0x3C
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`define ETH_MIISTATUS_ADR 8'hF // 0x3C
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`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
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`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
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`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
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`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
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`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_TX_CTRL_ADR 8'h14 // 0x50
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`define ETH_RX_CTRL_ADR 8'h15 // 0x54
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`define ETH_MODER_DEF 17'h0A800
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`define ETH_MODER_DEF 17'h0A800
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`define ETH_INT_MASK_DEF 7'h0
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`define ETH_INT_MASK_DEF 7'h0
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`define ETH_IPGT_DEF 7'h12
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`define ETH_IPGT_DEF 7'h12
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| Line 177... |
Line 183... |
`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR1_DEF 16'h0000
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`define ETH_MAC_ADDR1_DEF 16'h0000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_RX_CTRL_DEF 16'h0
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`define ETH_MODER_WIDTH 17
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`define ETH_MODER_WIDTH 17
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`define ETH_INT_SOURCE_WIDTH 7
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`define ETH_INT_SOURCE_WIDTH 7
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`define ETH_INT_MASK_WIDTH 7
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`define ETH_INT_MASK_WIDTH 7
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| Line 196... |
Line 203... |
`define ETH_MIISTATUS_WIDTH 3
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`define ETH_MIISTATUS_WIDTH 3
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`define ETH_MAC_ADDR0_WIDTH 32
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`define ETH_MAC_ADDR0_WIDTH 32
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`define ETH_MAC_ADDR1_WIDTH 16
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`define ETH_MAC_ADDR1_WIDTH 16
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`define ETH_HASH0_WIDTH 32
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`define ETH_HASH0_WIDTH 32
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`define ETH_HASH1_WIDTH 32
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`define ETH_HASH1_WIDTH 32
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`define ETH_TX_CTRL_WIDTH 17
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`define ETH_RX_CTRL_WIDTH 16
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// Outputs are registered (uncomment when needed)
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// Outputs are registered (uncomment when needed)
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`define ETH_REGISTERED_OUTPUTS
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`define ETH_REGISTERED_OUTPUTS
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