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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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`define ETH_FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements
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`define ETH_FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements
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// Should be cleared for the ASIC implementation
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// Should be cleared for the ASIC implementation
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// Address is {`ETHERNET_SPACE, REG_SPACE, 12'hx}
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`define ETH_ETHERNET_SPACE 16'hf000 // Ethernet space is allocated from 0xF0000000 to 0xF000FFFF
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`define ETH_MODER_ADR 6'h0 // 0x0
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`define ETH_REG_SPACE 4'h0 // Register space is allocated to 0xF0000000
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`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
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`define ETH_BD_SPACE 4'h1 // Buffer descriptor space is allocated to 0xF0001000
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`define ETH_INT_MASK_ADR 6'h2 // 0x8
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`define ETH_TX_DATA 4'h2 // Tx data is written to address 0xF0002000. Since DMA is used, TX_DATA is not used in equations.
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`define ETH_IPGT_ADR 6'h3 // 0xC
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`define ETH_RX_DATA 4'h3 // Rx data is read from address 0xF0003000. Since DMA is used, RX_DATA is not used in equations.
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`define ETH_IPGR1_ADR 6'h4 // 0x10
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`define ETH_IPGR2_ADR 6'h5 // 0x14
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`define ETH_PACKETLEN_ADR 6'h6 // 0x18
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`define ETH_PACKET_SEND_ADR 32'h20 // Packet for TX are written to the address 0x20
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`define ETH_COLLCONF_ADR 6'h7 // 0x1C
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`define ETH_RX_BD_ADR_ADR 6'h8 // 0x20
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`define ETH_MODER_ADR 6'h0
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`define ETH_CTRLMODER_ADR 6'h9 // 0x24
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`define ETH_INT_SOURCE_ADR 6'h1
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`define ETH_MIIMODER_ADR 6'hA // 0x28
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`define ETH_INT_MASK_ADR 6'h2
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`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
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`define ETH_IPGT_ADR 6'h3
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`define ETH_MIIADDRESS_ADR 6'hC // 0x30
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`define ETH_IPGR1_ADR 6'h4
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`define ETH_MIITX_DATA_ADR 6'hD // 0x34
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`define ETH_IPGR2_ADR 6'h5
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`define ETH_MIIRX_DATA_ADR 6'hE // 0x38
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`define ETH_PACKETLEN_ADR 6'h6
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`define ETH_MIISTATUS_ADR 6'hF // 0x3C
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`define ETH_COLLCONF_ADR 6'h7
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`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40
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`define ETH_RX_BD_ADR_ADR 6'h8
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`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44
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`define ETH_CTRLMODER_ADR 6'hA
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`define ETH_MIIMODER_ADR 6'hB
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`define ETH_MIICOMMAND_ADR 6'hC
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`define ETH_MIIADDRESS_ADR 6'hD
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`define ETH_MIITX_DATA_ADR 6'hE
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`define ETH_MIIRX_DATA_ADR 6'hF
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`define ETH_MIISTATUS_ADR 6'h10
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`define ETH_MAC_ADDR0_ADR 6'h11
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`define ETH_MAC_ADDR1_ADR 6'h12
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`define ETH_MODER_DEF 32'h0000A000
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`define ETH_MODER_DEF 32'h0000A000
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`define ETH_INT_SOURCE_DEF 32'h00000000
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`define ETH_INT_SOURCE_DEF 32'h00000000
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