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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 141 and 143

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Rev 141 Rev 143
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.18  2002/08/16 22:28:23  mohor
 
// Syntax error fixed.
 
//
// Revision 1.17  2002/08/16 22:23:03  mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
// Syntax error fixed.
// Syntax error fixed.
//
//
// Revision 1.16  2002/08/16 22:14:22  mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
Line 377... Line 380...
// TX_BD_NUM Register
// TX_BD_NUM Register
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
  (
  (
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
   .Write     (TX_BD_NUM_Wr),
   .Write     (TX_BD_NUM_Wr & (DataIn<='h80)),
   .Clk       (Clk),
   .Clk       (Clk),
   .Reset     (Reset),
   .Reset     (Reset),
   .SyncReset (1'b0)
   .SyncReset (1'b0)
  );
  );
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
Line 588... Line 591...
assign r_IFG              = MODEROut[6];
assign r_IFG              = MODEROut[6];
assign r_Pro              = MODEROut[5];
assign r_Pro              = MODEROut[5];
assign r_Iam              = MODEROut[4];
assign r_Iam              = MODEROut[4];
assign r_Bro              = MODEROut[3];
assign r_Bro              = MODEROut[3];
assign r_NoPre            = MODEROut[2];
assign r_NoPre            = MODEROut[2];
assign r_TxEn             = MODEROut[1];
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
assign r_RxEn             = MODEROut[0];
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
 
 
assign r_IPGT[6:0]        = IPGTOut[6:0];
assign r_IPGT[6:0]        = IPGTOut[6:0];
 
 
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
 
 

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