| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// instead of the number of RX descriptors).
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// instead of the number of RX descriptors).
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//
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//
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// Revision 1.5 2001/12/05 10:22:19 mohor
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// Revision 1.5 2001/12/05 10:22:19 mohor
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| Line 96... |
Line 99... |
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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r_HASH0, r_HASH1
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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input [5:0] Address;
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input [7:0] Address;
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input Rw;
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input Rw;
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input Cs;
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input Cs;
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input Clk;
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input Clk;
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input Reset;
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input Reset;
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| Line 172... |
Line 176... |
output [4:0] r_RGAD;
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output [4:0] r_RGAD;
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output [4:0] r_FIAD;
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output [4:0] r_FIAD;
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output [15:0]r_CtrlData;
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output [15:0]r_CtrlData;
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output [31:0]r_HASH0;
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output [31:0]r_HASH1;
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input NValid_stat;
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input NValid_stat;
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input Busy_stat;
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input Busy_stat;
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input LinkFail;
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input LinkFail;
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| Line 210... |
Line 217... |
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
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assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
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wire MAC_HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
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wire MAC_HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [31:0] INT_SOURCEOut;
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wire [31:0] INT_SOURCEOut;
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| Line 231... |
Line 240... |
wire [31:0] MIIRX_DATAOut;
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wire [31:0] MIIRX_DATAOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] MAC_HASH0Out;
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wire [31:0] MAC_HASH1Out;
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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| Line 267... |
Line 279... |
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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assign TX_BD_NUMOut[31:8] = 24'h0;
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assign TX_BD_NUMOut[31:8] = 24'h0;
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eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
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eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
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eth_register #(32) MAC_HASH0 (.DataIn(DataIn), .DataOut(MAC_HASH0Out), .Write(MAC_HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
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eth_register #(32) MAC_HASH1 (.DataIn(DataIn), .DataOut(MAC_HASH1Out), .Write(MAC_HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
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reg LinkFailRegister;
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reg LinkFailRegister;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q2;
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reg ResetLinkFailRegister_q2;
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| Line 297... |
Line 312... |
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always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
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always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
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IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
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IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
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MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
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MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
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MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
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MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
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TX_BD_NUMOut)
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TX_BD_NUMOut or MAC_HASH0Out or MAC_HASH1Out)
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begin
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begin
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if(Read) // read
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if(Read) // read
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begin
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begin
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case(Address)
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case(Address)
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`ETH_MODER_ADR : DataOut<=MODEROut;
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`ETH_MODER_ADR : DataOut<=MODEROut;
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| Line 320... |
Line 335... |
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
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`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
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`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
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`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
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`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
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`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
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`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
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`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
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`ETH_HASH0_ADR : DataOut<=MAC_HASH0Out;
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`ETH_HASH1_ADR : DataOut<=MAC_HASH1Out;
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default: DataOut<=32'h0;
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default: DataOut<=32'h0;
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endcase
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endcase
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end
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end
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else
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else
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DataOut<=32'h0;
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DataOut<=32'h0;
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| Line 389... |
Line 406... |
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
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assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
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assign r_HASH0 = MAC_HASH0Out;
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assign r_HASH1 = MAC_HASH1Out;
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// Interrupt generation
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// Interrupt generation
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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