URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 214 and 218

Rev 214	Rev 218
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.34 2002/10/10 16:49:50 mohor`
	`// Signals for WISHBONE B3 compliant interface added.`
	`//`
`// Revision 1.33 2002/10/10 16:29:30 mohor`	`// Revision 1.33 2002/10/10 16:29:30 mohor`
`// BIST added.`	`// BIST added.`
`//`	`//`
`// Revision 1.32 2002/09/20 17:12:58 mohor`	`// Revision 1.32 2002/09/20 17:12:58 mohor`
`// CsMiss added. When address between 0x800 and 0xfff is accessed within`	`// CsMiss added. When address between 0x800 and 0xfff is accessed within`
Line 753...	Line 756...
`.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)`	`.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)`

`ifdef ETH_BIST	`ifdef ETH_BIST
`,`	`,`
`.trst(trst), .SO(SO), .SI(SI),`	`.trst(trst), .SO(SO), .SI(SI),`
`.shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest),`	`.shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest),`
`.tck(tck)`	`.tck(tck)`
`endif	`endif
`);`	`);`