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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  eth_txethmac.v                                              ////
////  eth_txethmac.v                                              ////
///                                                              ////
///                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/02/22 12:56:35  mohor
// Revision 1.6  2002/02/22 12:56:35  mohor
// Retry is not activated when a Tx Underrun occured
// Retry is not activated when a Tx Underrun occured
//
//
// Revision 1.5  2002/02/11 09:18:22  mohor
// Revision 1.5  2002/02/11 09:18:22  mohor
// Tx status is written back to the BD.
// Tx status is written back to the BD.
//
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
//
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
// simulation of the few cores in a one joined project.
//
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
// Few little NCSIM warnings fixed.
//
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
// is done due to the ASIC tools.
//
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
// Directory structure changed. Files checked and joind together.
//
//
// Revision 1.3  2001/06/19 18:16:40  mohor
// Revision 1.3  2001/06/19 18:16:40  mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
// Crc changed so only one file can be used instead of two.
//
//
// Revision 1.2  2001/06/19 10:38:08  mohor
// Revision 1.2  2001/06/19 10:38:08  mohor
// Minor changes in header.
// Minor changes in header.
//
//
// Revision 1.1  2001/06/19 10:27:58  mohor
// Revision 1.1  2001/06/19 10:27:58  mohor
// TxEthMAC initial release.
// TxEthMAC initial release.
//
//
//
//
//
//
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
                     LateCollision, StartDefer, StatePreamble, StateData
                     LateCollision, StartDefer, StatePreamble, StateData
 
 
                    );
                    );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
 
 
input MTxClk;                   // Transmit clock (from PHY)
input MTxClk;                   // Transmit clock (from PHY)
input Reset;                    // Reset
input Reset;                    // Reset
input TxStartFrm;               // Transmit packet start frame
input TxStartFrm;               // Transmit packet start frame
input TxEndFrm;                 // Transmit packet end frame
input TxEndFrm;                 // Transmit packet end frame
input TxUnderRun;               // Transmit packet under-run
input TxUnderRun;               // Transmit packet under-run
input [7:0] TxData;             // Transmit packet data byte
input [7:0] TxData;             // Transmit packet data byte
input CarrierSense;             // Carrier sense (synchronized)
input CarrierSense;             // Carrier sense (synchronized)
input Collision;                // Collision (synchronized)
input Collision;                // Collision (synchronized)
input Pad;                      // Pad enable (from register)
input Pad;                      // Pad enable (from register)
input CrcEn;                    // Crc enable (from register)
input CrcEn;                    // Crc enable (from register)
input FullD;                    // Full duplex (from register)
input FullD;                    // Full duplex (from register)
input HugEn;                    // Huge packets enable (from register)
input HugEn;                    // Huge packets enable (from register)
input DlyCrcEn;                 // Delayed Crc enabled (from register)
input DlyCrcEn;                 // Delayed Crc enabled (from register)
input [15:0] MinFL;             // Minimum frame length (from register)
input [15:0] MinFL;             // Minimum frame length (from register)
input [15:0] MaxFL;             // Maximum frame length (from register)
input [15:0] MaxFL;             // Maximum frame length (from register)
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid;          // Valid collision window (from register)
input [5:0] CollValid;          // Valid collision window (from register)
input [3:0] MaxRet;             // Maximum retry number (from register)
input [3:0] MaxRet;             // Maximum retry number (from register)
input NoBckof;                  // No backoff (from register)
input NoBckof;                  // No backoff (from register)
input ExDfrEn;                  // Excessive defferal enable (from register)
input ExDfrEn;                  // Excessive defferal enable (from register)
 
 
output [3:0] MTxD;              // Transmit nibble (to PHY)
output [3:0] MTxD;              // Transmit nibble (to PHY)
output MTxEn;                   // Transmit enable (to PHY)
output MTxEn;                   // Transmit enable (to PHY)
output MTxErr;                  // Transmit error (to PHY)
output MTxErr;                  // Transmit error (to PHY)
output TxDone;                  // Transmit packet done (to RISC)
output TxDone;                  // Transmit packet done (to RISC)
output TxRetry;                 // Transmit packet retry (to RISC)
output TxRetry;                 // Transmit packet retry (to RISC)
output TxAbort;                 // Transmit packet abort (to RISC)
output TxAbort;                 // Transmit packet abort (to RISC)
output TxUsedData;              // Transmit packet used data (to RISC)
output TxUsedData;              // Transmit packet used data (to RISC)
output WillTransmit;            // Will transmit (to RxEthMAC)
output WillTransmit;            // Will transmit (to RxEthMAC)
output ResetCollision;          // Reset Collision (for synchronizing collision)
output ResetCollision;          // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxDone;
output StartTxAbort;
output StartTxAbort;
output MaxCollisionOccured;
output MaxCollisionOccured;
output LateCollision;
output LateCollision;
output StartDefer;
output StartDefer;
output StatePreamble;
output StatePreamble;
output [1:0] StateData;
output [1:0] StateData;
 
 
reg [3:0] MTxD;
reg [3:0] MTxD;
reg MTxEn;
reg MTxEn;
reg MTxErr;
reg MTxErr;
reg TxDone;
reg TxDone;
reg TxRetry;
reg TxRetry;
reg TxAbort;
reg TxAbort;
reg TxUsedData;
reg TxUsedData;
reg WillTransmit;
reg WillTransmit;
reg ColWindow;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg [3:0] MTxD_d;
reg StatusLatch;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished_q;
reg PacketFinished;
reg PacketFinished;
 
 
 
 
wire ExcessiveDeferOccured;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartIPG;
wire StartPreamble;
wire StartPreamble;
wire [1:0] StartData;
wire [1:0] StartData;
wire StartFCS;
wire StartFCS;
wire StartJam;
wire StartJam;
wire StartBackoff;
wire StartBackoff;
wire StateDefer;
wire StateDefer;
wire StateIPG;
wire StateIPG;
wire StateIdle;
wire StateIdle;
wire StatePAD;
wire StatePAD;
wire StateFCS;
wire StateFCS;
wire StateJam;
wire StateJam;
wire StateBackOff;
wire StateBackOff;
wire StateSFD;
wire StateSFD;
wire StartTxRetry;
wire StartTxRetry;
wire UnderRun;
wire UnderRun;
wire TooBig;
wire TooBig;
wire [31:0] Crc;
wire [31:0] Crc;
wire CrcError;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq7;
wire NibCntEq15;
wire NibCntEq15;
wire NibbleMinFl;
wire NibbleMinFl;
wire ExcessiveDefer;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire [15:0] ByteCnt;
wire MaxFrame;
wire MaxFrame;
wire RetryMax;
wire RetryMax;
wire RandomEq0;
wire RandomEq0;
wire RandomEqByteCnt;
wire RandomEqByteCnt;
wire PacketFinished_d;
wire PacketFinished_d;
 
 
 
 
 
 
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
 
 
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
 
 
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
 
 
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
 
 
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
 
 
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
 
 
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
 
 
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
 
 
assign StateSFD = StatePreamble & NibCntEq15;
assign StateSFD = StatePreamble & NibCntEq15;
 
 
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
 
 
 
 
// StopExcessiveDeferOccured
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    StopExcessiveDeferOccured <= #Tp 1'b0;
    StopExcessiveDeferOccured <= #Tp 1'b0;
  else
  else
    begin
    begin
      if(~TxStartFrm)
      if(~TxStartFrm)
        StopExcessiveDeferOccured <= #Tp 1'b0;
        StopExcessiveDeferOccured <= #Tp 1'b0;
      else
      else
      if(ExcessiveDeferOccured)
      if(ExcessiveDeferOccured)
        StopExcessiveDeferOccured <= #Tp 1'b1;
        StopExcessiveDeferOccured <= #Tp 1'b1;
    end
    end
end
end
 
 
 
 
// Collision Window
// Collision Window
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ColWindow <= #Tp 1'b1;
    ColWindow <= #Tp 1'b1;
  else
  else
    begin
    begin
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
        ColWindow <= #Tp 1'b0;
        ColWindow <= #Tp 1'b0;
      else
      else
      if(StateIdle | StateIPG)
      if(StateIdle | StateIPG)
        ColWindow <= #Tp 1'b1;
        ColWindow <= #Tp 1'b1;
    end
    end
end
end
 
 
 
 
// Start Window
// Start Window
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    StatusLatch <= #Tp 1'b0;
    StatusLatch <= #Tp 1'b0;
  else
  else
    begin
    begin
      if(~TxStartFrm)
      if(~TxStartFrm)
        StatusLatch <= #Tp 1'b0;
        StatusLatch <= #Tp 1'b0;
      else
      else
      if(ExcessiveDeferOccured | StateIdle)
      if(ExcessiveDeferOccured | StateIdle)
        StatusLatch <= #Tp 1'b1;
        StatusLatch <= #Tp 1'b1;
     end
     end
end
end
 
 
 
 
// Transmit packet used data
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxUsedData <= #Tp 1'b0;
    TxUsedData <= #Tp 1'b0;
  else
  else
    TxUsedData <= #Tp |StartData;
    TxUsedData <= #Tp |StartData;
end
end
 
 
 
 
// Transmit packet done
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxDone <= #Tp 1'b0;
    TxDone <= #Tp 1'b0;
  else
  else
    begin
    begin
      if(TxStartFrm & ~StatusLatch)
      if(TxStartFrm & ~StatusLatch)
        TxDone <= #Tp 1'b0;
        TxDone <= #Tp 1'b0;
      else
      else
      if(StartTxDone)
      if(StartTxDone)
        TxDone <= #Tp 1'b1;
        TxDone <= #Tp 1'b1;
    end
    end
end
end
 
 
 
 
// Transmit packet retry
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxRetry <= #Tp 1'b0;
    TxRetry <= #Tp 1'b0;
  else
  else
    begin
    begin
      if(TxStartFrm & ~StatusLatch)
      if(TxStartFrm & ~StatusLatch)
        TxRetry <= #Tp 1'b0;
        TxRetry <= #Tp 1'b0;
      else
      else
      if(StartTxRetry)
      if(StartTxRetry)
        TxRetry <= #Tp 1'b1;
        TxRetry <= #Tp 1'b1;
     end
     end
end
end
 
 
 
 
// Transmit packet abort
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxAbort <= #Tp 1'b0;
    TxAbort <= #Tp 1'b0;
  else
  else
    begin
    begin
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
        TxAbort <= #Tp 1'b0;
        TxAbort <= #Tp 1'b0;
      else
      else
      if(StartTxAbort)
      if(StartTxAbort)
        TxAbort <= #Tp 1'b1;
        TxAbort <= #Tp 1'b1;
    end
    end
end
end
 
 
 
 
// Retry counter
// Retry counter
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RetryCnt[3:0] <= #Tp 4'h0;
    RetryCnt[3:0] <= #Tp 4'h0;
  else
  else
    begin
    begin
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
        RetryCnt[3:0] <= #Tp 4'h0;
        RetryCnt[3:0] <= #Tp 4'h0;
      else
      else
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
    end
    end
end
end
 
 
 
 
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
 
 
 
 
// Transmit nibble
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
          Crc or NibCnt or NibCntEq15)
          Crc or NibCnt or NibCntEq15)
begin
begin
  if(StateData[0])
  if(StateData[0])
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
  else
  else
  if(StateData[1])
  if(StateData[1])
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
  else
  else
  if(StateFCS)
  if(StateFCS)
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
  else
  else
  if(StateJam)
  if(StateJam)
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
  else
  else
  if(StatePreamble)
  if(StatePreamble)
    if(NibCntEq15)
    if(NibCntEq15)
      MTxD_d[3:0] = 4'hd;                                       // SFD
      MTxD_d[3:0] = 4'hd;                                       // SFD
    else
    else
      MTxD_d[3:0] = 4'h5;                                       // Preamble
      MTxD_d[3:0] = 4'h5;                                       // Preamble
  else
  else
    MTxD_d[3:0] = 4'h0;
    MTxD_d[3:0] = 4'h0;
end
end
 
 
 
 
// Transmit Enable
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    MTxEn <= #Tp 1'b0;
    MTxEn <= #Tp 1'b0;
  else
  else
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
end
 
 
 
 
// Transmit nibble
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    MTxD[3:0] <= #Tp 4'h0;
    MTxD[3:0] <= #Tp 4'h0;
  else
  else
    MTxD[3:0] <= #Tp MTxD_d[3:0];
    MTxD[3:0] <= #Tp MTxD_d[3:0];
end
end
 
 
 
 
// Transmit error
// Transmit error
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    MTxErr <= #Tp 1'b0;
    MTxErr <= #Tp 1'b0;
  else
  else
    MTxErr <= #Tp TooBig | UnderRun;
    MTxErr <= #Tp TooBig | UnderRun;
end
end
 
 
 
 
// WillTransmit
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    WillTransmit <= #Tp  1'b0;
    WillTransmit <= #Tp  1'b0;
  else
  else
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
end
 
 
 
 
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
 
 
 
 
// Packet finished
// Packet finished
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      PacketFinished <= #Tp 1'b0;
      PacketFinished <= #Tp 1'b0;
      PacketFinished_q  <= #Tp 1'b0;
      PacketFinished_q  <= #Tp 1'b0;
    end
    end
  else
  else
    begin
    begin
      PacketFinished <= #Tp PacketFinished_d;
      PacketFinished <= #Tp PacketFinished_d;
      PacketFinished_q  <= #Tp PacketFinished;
      PacketFinished_q  <= #Tp PacketFinished;
    end
    end
end
end
 
 
 
 
// Connecting module Counters
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
                            .DlyCrcCnt(DlyCrcCnt)
                            .DlyCrcCnt(DlyCrcCnt)
                           );
                           );
 
 
 
 
// Connecting module StateM
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
                        .StartDefer(StartDefer), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
                        .StartDefer(StartDefer), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
                       );
                       );
 
 
 
 
wire Enable_Crc;
wire Enable_Crc;
wire [3:0] Data_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
wire Initialize_Crc;
 
 
assign Enable_Crc = ~StateFCS;
assign Enable_Crc = ~StateFCS;
 
 
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
 
 
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
 
 
 
 
// Connecting module Crc
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
               .Crc(Crc), .CrcError(CrcError)
               .Crc(Crc), .CrcError(CrcError)
              );
              );
 
 
 
 
// Connecting module Random
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
 
 
 
 
 
 
 
 
endmodule
endmodule
 
 

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