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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 106 and 110

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Rev 106 Rev 110
Line 39... Line 39... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.23  2002/05/03 10:15:50  mohor
 
 
 
// Outputs registered. Reset changed for eth_wishbone module.
 
 
 
//
 
// Revision 1.22  2002/04/24 08:52:19  mohor
 
// Revision 1.22  2002/04/24 08:52:19  mohor
 
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
 
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
 
// bug fixed.
 
// bug fixed.
 
//
 
//
 
// Revision 1.21  2002/03/29 16:18:11  lampret
 
// Revision 1.21  2002/03/29 16:18:11  lampret
Line 164... Line 167... 
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
 
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
 
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
 
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
 
 
 
 
 
    // Tx Status
 
    // Tx Status
 
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
 
 
 
 
                );
 
                );
 
 
 
 
 
 
 
 
 
parameter Tp = 1;
 
parameter Tp = 1;
 
 
 
 
Line 426... Line 430... 
  else
 
  else
 
  if(TxPointerRead & TxEn & TxEn_q)
 
  if(TxPointerRead & TxEn & TxEn_q)
 
    TxEn_needed <=#Tp 1'b0;
 
    TxEn_needed <=#Tp 1'b0;
 
end
 
end
 
 
 
 
 
reg [3:0] stm_status;
 
 
 
// Enabling access to the RAM for three devices.
 
// Enabling access to the RAM for three devices.
 
always @ (posedge WB_CLK_I or posedge Reset)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    begin
 
    begin
Line 439... Line 442... 
      TxEn <=#Tp 1'b0;
 
      TxEn <=#Tp 1'b0;
 
      ram_addr <=#Tp 8'h0;
 
      ram_addr <=#Tp 8'h0;
 
      ram_di <=#Tp 32'h0;
 
      ram_di <=#Tp 32'h0;
 
      BDRead <=#Tp 1'b0;
 
      BDRead <=#Tp 1'b0;
 
      BDWrite <=#Tp 1'b0;
 
      BDWrite <=#Tp 1'b0;
 
stm_status <=#Tp 4'h0;
 
 
 
    end
 
    end
 
  else
 
  else
 
    begin
 
    begin
 
      // Switching between three stages depends on enable signals
 
      // Switching between three stages depends on enable signals
 
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
 
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
 
        5'b100_10, 5'b100_11 :
 
        5'b100_10, 5'b100_11 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h1;
 
 
 
            WbEn <=#Tp 1'b0;
 
            WbEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
 
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
 
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
 
            ram_di <=#Tp RxBDDataIn;
 
            ram_di <=#Tp RxBDDataIn;
 
          end
 
          end
 
        5'b100_01 :
 
        5'b100_01 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h2;
 
 
 
            WbEn <=#Tp 1'b0;
 
            WbEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
 
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_di <=#Tp TxBDDataIn;
 
            ram_di <=#Tp TxBDDataIn;
 
          end
 
          end
 
        5'b010_00, 5'b010_10 :
 
        5'b010_00, 5'b010_10 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h3;
 
 
 
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
 
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
          end
 
          end
 
        5'b010_01, 5'b010_11 :
 
        5'b010_01, 5'b010_11 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h4;
 
 
 
            WbEn <=#Tp 1'b0;
 
            WbEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
 
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
 
            ram_di <=#Tp TxBDDataIn;
 
            ram_di <=#Tp TxBDDataIn;
 
          end
 
          end
 
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
 
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h5;
 
 
 
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
 
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
          end
 
          end
 
        5'b100_00 :
 
        5'b100_00 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h6;
 
 
 
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
 
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
 
          end
 
          end
 
        5'b000_00 :
 
        5'b000_00 :
 
          begin
 
          begin
 
stm_status <=#Tp 4'h7;
 
 
 
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
 
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
 
            RxEn <=#Tp 1'b0;
 
            RxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            TxEn <=#Tp 1'b0;
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
            ram_di <=#Tp WB_DAT_I;
 
            ram_di <=#Tp WB_DAT_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
          end
 
          end
 
        default :
 
 
 
          begin
 
 
 
            WbEn <=#Tp 1'b1;  // We go to wb access stage
 
 
 
            RxEn <=#Tp 1'b0;
 
 
 
            TxEn <=#Tp 1'b0;
 
 
 
            ram_addr <=#Tp WB_ADR_I[9:2];
 
 
 
            ram_di <=#Tp WB_DAT_I;
 
 
 
            BDWrite <=#Tp BDCs & WB_WE_I;
 
 
 
            BDRead <=#Tp BDCs & ~WB_WE_I;
 
 
 
          end
 
 
 
      endcase
 
      endcase
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
Line 573... Line 558... 
    TxBDReady <=#Tp 1'b0;
 
    TxBDReady <=#Tp 1'b0;
 
end
 
end
 
 
 
 
 
 
 
 
 
// Reading the Tx buffer descriptor
 
// Reading the Tx buffer descriptor
 
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead;
 
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    TxBDRead <=#Tp 1'b1;
 
    TxBDRead <=#Tp 1'b1;
 
  else
 
  else
 
  if(StartTxBDRead & ~TxBDReady)
 
  if(StartTxBDRead)
 
    TxBDRead <=#Tp 1'b1;
 
    TxBDRead <=#Tp 1'b1;
 
  else
 
  else
 
  if(TxBDReady)
 
  if(TxBDReady)
 
    TxBDRead <=#Tp 1'b0;
 
    TxBDRead <=#Tp 1'b0;
 
end
 
end
Line 630... Line 615... 
always @ (posedge WB_CLK_I or posedge Reset)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    BlockingTxBDRead <=#Tp 1'b0;
 
    BlockingTxBDRead <=#Tp 1'b0;
 
  else
 
  else
 
  if(StartTxBDRead & ~TxBDReady)
 
  if(StartTxBDRead)
 
    BlockingTxBDRead <=#Tp 1'b1;
 
    BlockingTxBDRead <=#Tp 1'b1;
 
  else
 
  else
 
  if(TxStartFrm_wb)
 
  if(~StartTxBDRead & ~TxBDReady)
 
    BlockingTxBDRead <=#Tp 1'b0;
 
    BlockingTxBDRead <=#Tp 1'b0;
 
end
 
end
 
 
 
 
 
 
 
 
 
// Latching status from the tx buffer descriptor
 
// Latching status from the tx buffer descriptor
Line 831... Line 816... 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
 
 
 
reg cyc_cleared;
 
//assign m_wb_sel_o = 4'hf;
 
 
 
 
 
 
 
// Enabling master wishbone access to the memory for two devices TX and RX.
 
// Enabling master wishbone access to the memory for two devices TX and RX.
 
always @ (posedge WB_CLK_I or posedge Reset)
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
Line 846... Line 830... 
      m_wb_adr_o <=#Tp 32'h0;
 
      m_wb_adr_o <=#Tp 32'h0;
 
      m_wb_cyc_o <=#Tp 1'b0;
 
      m_wb_cyc_o <=#Tp 1'b0;
 
      m_wb_stb_o <=#Tp 1'b0;
 
      m_wb_stb_o <=#Tp 1'b0;
 
      m_wb_we_o  <=#Tp 1'b0;
 
      m_wb_we_o  <=#Tp 1'b0;
 
      m_wb_sel_o <=#Tp 4'h0;
 
      m_wb_sel_o <=#Tp 4'h0;
 
 
 
      cyc_cleared<=#Tp 1'b0;
 
    end
 
    end
 
  else
 
  else
 
    begin
 
    begin
 
      // Switching between two stages depends on enable signals
 
      // Switching between two stages depends on enable signals
 
      case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})  // synopsys parallel_case
 
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared})  // synopsys parallel_case
 
        5'b00_01_0, 5'b00_11_0 :
 
        6'b00_01_0_x, 6'b00_11_0_x :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
 
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
 
            MasterWbRX <=#Tp 1'b1;
 
            MasterWbRX <=#Tp 1'b1;
 
            m_wb_adr_o <=#Tp RxPointer;
 
            m_wb_adr_o <=#Tp RxPointer;
 
            m_wb_cyc_o <=#Tp 1'b1;
 
            m_wb_cyc_o <=#Tp 1'b1;
 
            m_wb_stb_o <=#Tp 1'b1;
 
            m_wb_stb_o <=#Tp 1'b1;
 
            m_wb_we_o  <=#Tp 1'b1;
 
            m_wb_we_o  <=#Tp 1'b1;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
 
          end
 
          end
 
        5'b00_10_0, 5'b00_10_1 :
 
        6'b00_10_0_x, 6'b00_10_1_x :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
 
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
 
            MasterWbRX <=#Tp 1'b0;
 
            MasterWbRX <=#Tp 1'b0;
 
            m_wb_adr_o <=#Tp TxPointer;
 
            m_wb_adr_o <=#Tp TxPointer;
 
            m_wb_cyc_o <=#Tp 1'b1;
 
            m_wb_cyc_o <=#Tp 1'b1;
 
            m_wb_stb_o <=#Tp 1'b1;
 
            m_wb_stb_o <=#Tp 1'b1;
 
            m_wb_we_o  <=#Tp 1'b0;
 
            m_wb_we_o  <=#Tp 1'b0;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
 
          end
 
          end
 
        5'b10_10_1 :
 
        6'b10_10_0_1 :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
 
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
 
            MasterWbRX <=#Tp 1'b0;
 
            MasterWbRX <=#Tp 1'b0;
 
            m_wb_adr_o <=#Tp TxPointer;
 
            m_wb_adr_o <=#Tp TxPointer;
 
            m_wb_cyc_o <=#Tp 1'b1;
 
            m_wb_cyc_o <=#Tp 1'b1;
 
            m_wb_stb_o <=#Tp 1'b1;
 
            m_wb_stb_o <=#Tp 1'b1;
 
            m_wb_we_o  <=#Tp 1'b0;
 
            m_wb_we_o  <=#Tp 1'b0;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
 
 
 
            cyc_cleared<=#Tp 1'b0;
 
          end
 
          end
 
        5'b01_01_1 :
 
        6'b01_01_0_1 :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
 
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
 
            MasterWbRX <=#Tp 1'b1;
 
            MasterWbRX <=#Tp 1'b1;
 
            m_wb_adr_o <=#Tp RxPointer;
 
            m_wb_adr_o <=#Tp RxPointer;
 
            m_wb_we_o  <=#Tp 1'b1;
 
            m_wb_we_o  <=#Tp 1'b1;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
 
 
 
            cyc_cleared<=#Tp 1'b0;
 
          end
 
          end
 
        5'b10_01_1, 5'b10_11_1 :
 
        6'b10_01_0_1, 6'b10_11_0_1 :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
 
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
 
            MasterWbRX <=#Tp 1'b1;
 
            MasterWbRX <=#Tp 1'b1;
 
            m_wb_adr_o <=#Tp RxPointer;
 
            m_wb_adr_o <=#Tp RxPointer;
 
            m_wb_we_o  <=#Tp 1'b1;
 
            m_wb_we_o  <=#Tp 1'b1;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
 
 
 
            cyc_cleared<=#Tp 1'b0;
 
          end
 
          end
 
        5'b01_10_1, 5'b01_11_1 :
 
        6'b01_10_1_0, 6'b01_11_0_1 :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
 
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
 
            MasterWbRX <=#Tp 1'b0;
 
            MasterWbRX <=#Tp 1'b0;
 
            m_wb_adr_o <=#Tp TxPointer;
 
            m_wb_adr_o <=#Tp TxPointer;
 
            m_wb_we_o  <=#Tp 1'b0;
 
            m_wb_we_o  <=#Tp 1'b0;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
 
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
 
 
 
            cyc_cleared<=#Tp 1'b0;
 
 
 
          end
 
 
 
        6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
 
 
 
          begin
 
 
 
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
 
 
 
            m_wb_stb_o <=#Tp 1'b0;
 
 
 
            cyc_cleared<=#Tp 1'b1;
 
          end
 
          end
 
        5'b10_00_1, 5'b01_00_1 :
 
        6'b10_00_1_x, 6'b01_00_1_x :
 
          begin
 
          begin
 
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
 
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
 
            MasterWbRX <=#Tp 1'b0;
 
            MasterWbRX <=#Tp 1'b0;
 
            m_wb_cyc_o <=#Tp 1'b0;
 
            m_wb_cyc_o <=#Tp 1'b0;
 
            m_wb_stb_o <=#Tp 1'b0;
 
            m_wb_stb_o <=#Tp 1'b0;
Line 924... Line 919... 
          end
 
          end
 
      endcase
 
      endcase
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
wire TxFifoClear;
 
wire TxFifoClear;
 
wire [31:0] tx_fifo_dat_i;
 
wire [31:0] tx_fifo_dat_i;
 
 
 
 
 
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
 
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
 
 
 
 
Line 2085... Line 2082... 
// bit 12 od rx je reserved
 
// bit 12 od rx je reserved
 
// bit 11 od rx je reserved
 
// bit 11 od rx je reserved
 
// bit 10 od rx je reserved
 
// bit 10 od rx je reserved
 
// bit 9  od rx je reserved
 
// bit 9  od rx je reserved
 
// bit 8  od rx je reserved
 
// bit 8  od rx je reserved
 
// bit 7  od rx je Miss               still needs to be done
 
// bit 7  od rx je Miss
 
// bit 6  od rx je RxOverrun
 
// bit 6  od rx je RxOverrun
 
// bit 5  od rx je InvalidSymbol
 
// bit 5  od rx je InvalidSymbol
 
// bit 4  od rx je DribbleNibble
 
// bit 4  od rx je DribbleNibble
 
// bit 3  od rx je ReceivedPacketTooBig
 
// bit 3  od rx je ReceivedPacketTooBig
 
// bit 2  od rx je ShortFrame
 
// bit 2  od rx je ShortFrame
 
// bit 1  od rx je LatchedCrcError
 
// bit 1  od rx je LatchedCrcError
 
// bit 0  od rx je RxLateCollision
 
// bit 0  od rx je RxLateCollision
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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