| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2002/07/25 18:29:01 mohor
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// WriteRxDataToMemory signal changed so end of frame (when last word is
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// written to fifo) is changed.
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//
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// Revision 1.30 2002/07/23 15:28:31 mohor
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// Revision 1.30 2002/07/23 15:28:31 mohor
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// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
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// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
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//
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//
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// Revision 1.29 2002/07/20 00:41:32 mohor
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// Revision 1.29 2002/07/20 00:41:32 mohor
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// ShiftEnded synchronization changed.
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// ShiftEnded synchronization changed.
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| Line 1135... |
Line 1139... |
assign WrapRxStatusBit = RxStatus[13];
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assign WrapRxStatusBit = RxStatus[13];
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// Temporary Tx and Rx buffer descriptor address
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// Temporary Tx and Rx buffer descriptor address
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assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
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assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
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assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD
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assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1) | // Using first Rx BD
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{8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
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{8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
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// Latching Tx buffer descriptor address
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// Latching Tx buffer descriptor address
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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| Line 1154... |
Line 1158... |
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// Latching Rx buffer descriptor address
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// Latching Rx buffer descriptor address
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF;
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RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
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else
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else
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
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RxBDAddress <=#Tp WB_DAT_I[7:0];
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RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
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else
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else
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if(RxStatusWrite)
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if(RxStatusWrite)
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RxBDAddress <=#Tp TempRxBDAddress;
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RxBDAddress <=#Tp TempRxBDAddress;
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end
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end
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