| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.32 2002/08/14 19:31:48 mohor
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// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
|
|
// need to multiply or devide any more.
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|
//
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// Revision 1.31 2002/07/25 18:29:01 mohor
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// Revision 1.31 2002/07/25 18:29:01 mohor
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// WriteRxDataToMemory signal changed so end of frame (when last word is
|
// WriteRxDataToMemory signal changed so end of frame (when last word is
|
// written to fifo) is changed.
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// written to fifo) is changed.
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//
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//
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// Revision 1.30 2002/07/23 15:28:31 mohor
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// Revision 1.30 2002/07/23 15:28:31 mohor
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| Line 173... |
Line 177... |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
|
|
|
//TX
|
//TX
|
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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PerPacketPad,
|
PerPacketPad,
|
|
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//RX
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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|
|
// Register
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RecSmall,
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
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|
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WillSendControlFrame, TxCtrlEndFrm, // WillSendControlFrame out ?
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|
|
|
// Interrupts
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
|
|
|
// Rx Status
|
// Rx Status
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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|
|
// Tx Status
|
// Tx Status
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost,
|
|
|
|
reg1, reg2, reg3, reg4
|
|
|
);
|
);
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|
|
|
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parameter Tp = 1;
|
parameter Tp = 1;
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|
|
|
output [31:0] reg1, reg2, reg3, reg4;
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|
|
// WISHBONE common
|
// WISHBONE common
|
input WB_CLK_I; // WISHBONE clock
|
input WB_CLK_I; // WISHBONE clock
|
input [31:0] WB_DAT_I; // WISHBONE data input
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input [31:0] WB_DAT_I; // WISHBONE data input
|
output [31:0] WB_DAT_O; // WISHBONE data output
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output [31:0] WB_DAT_O; // WISHBONE data output
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| Line 253... |
Line 259... |
output TxEndFrm; // Transmit packet end frame
|
output TxEndFrm; // Transmit packet end frame
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output [7:0] TxData; // Transmit packet data byte
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output [7:0] TxData; // Transmit packet data byte
|
output TxUnderRun; // Transmit packet under-run
|
output TxUnderRun; // Transmit packet under-run
|
output PerPacketCrcEn; // Per packet crc enable
|
output PerPacketCrcEn; // Per packet crc enable
|
output PerPacketPad; // Per packet pading
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output PerPacketPad; // Per packet pading
|
output TPauseRq; // Tx PAUSE control frame
|
|
output [15:0] TxPauseTV; // PAUSE timer value
|
|
input WillSendControlFrame;
|
|
input TxCtrlEndFrm;
|
|
|
|
// Rx
|
// Rx
|
input MRxClk; // Receive clock (from PHY)
|
input MRxClk; // Receive clock (from PHY)
|
input [7:0] RxData; // Received data byte (from PHY)
|
input [7:0] RxData; // Received data byte (from PHY)
|
input RxValid; //
|
input RxValid; //
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| Line 271... |
Line 273... |
//Register
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//Register
|
input r_TxEn; // Transmit enable
|
input r_TxEn; // Transmit enable
|
input r_RxEn; // Receive enable
|
input r_RxEn; // Receive enable
|
input [7:0] r_TxBDNum; // Receive buffer descriptor number
|
input [7:0] r_TxBDNum; // Receive buffer descriptor number
|
input TX_BD_NUM_Wr; // RxBDNumber written
|
input TX_BD_NUM_Wr; // RxBDNumber written
|
input r_RecSmall; // Receive small frames igor !!! tega uporabi
|
|
|
|
// Interrupts
|
// Interrupts
|
output TxB_IRQ;
|
output TxB_IRQ;
|
output TxE_IRQ;
|
output TxE_IRQ;
|
output RxB_IRQ;
|
output RxB_IRQ;
|
output RxE_IRQ;
|
output RxE_IRQ;
|
output Busy_IRQ;
|
output Busy_IRQ;
|
output TxC_IRQ;
|
|
output RxC_IRQ;
|
|
|
|
|
|
reg TxB_IRQ;
|
reg TxB_IRQ;
|
reg TxE_IRQ;
|
reg TxE_IRQ;
|
reg RxB_IRQ;
|
reg RxB_IRQ;
|
| Line 675... |
Line 674... |
reg m_wb_we_o;
|
reg m_wb_we_o;
|
|
|
wire TxLengthEq0;
|
wire TxLengthEq0;
|
wire TxLengthLt4;
|
wire TxLengthLt4;
|
|
|
wire WordAccFinished;
|
reg BlockingIncrementTxPointer;
|
wire HalfAccFinished;
|
reg [31:0] TxPointer;
|
|
reg [1:0] TxPointerLatched;
|
|
reg [1:0] TxPointerLatched_rst;
|
|
reg [31:0] RxPointer;
|
|
reg [1:0] RxPointerLatched;
|
|
|
|
wire RxBurstAcc;
|
|
wire RxWordAcc;
|
|
wire RxHalfAcc;
|
|
wire RxByteAcc;
|
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 691... |
Line 699... |
else
|
else
|
if(MasterWbTX & m_wb_ack_i)
|
if(MasterWbTX & m_wb_ack_i)
|
begin
|
begin
|
if(TxLengthLt4)
|
if(TxLengthLt4)
|
TxLength <=#Tp 16'h0;
|
TxLength <=#Tp 16'h0;
|
else if(WordAccFinished)
|
else
|
|
if(TxPointerLatched_rst==2'h0)
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
else if(HalfAccFinished)
|
|
TxLength <=#Tp TxLength - 2'h2; // Length is subtracted at the data request
|
|
else
|
else
|
TxLength <=#Tp TxLength - 1'h1; // Length is subtracted at the data request
|
if(TxPointerLatched_rst==2'h1)
|
|
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
|
|
else
|
|
if(TxPointerLatched_rst==2'h2)
|
|
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
|
|
else
|
|
if(TxPointerLatched_rst==2'h3)
|
|
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
|
end
|
end
|
end
|
end
|
|
|
assign WordAccFinished = &m_wb_sel_o[3:0];
|
|
assign HalfAccFinished = &m_wb_sel_o[1:0];
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|
|
|
|
|
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 718... |
Line 729... |
end
|
end
|
|
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthLt4 = TxLength < 4;
|
assign TxLengthLt4 = TxLength < 4;
|
|
|
|
reg cyc_cleared;
|
reg BlockingIncrementTxPointer;
|
reg IncrTxPointer;
|
|
|
reg [31:0] TxPointer;
|
|
reg [1:0] TxPointerLatched;
|
|
reg [31:0] RxPointer;
|
|
reg [1:0] RxPointerLatched;
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|
|
|
wire TxBurstAcc;
|
|
wire TxWordAcc;
|
|
wire TxHalfAcc;
|
|
wire TxByteAcc;
|
|
|
|
wire RxBurstAcc;
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wire RxWordAcc;
|
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wire RxHalfAcc;
|
|
wire RxByteAcc;
|
|
|
|
|
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//Latching Tx buffer pointer from buffer descriptor;
|
//Latching Tx buffer pointer from buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 746... |
Line 742... |
TxPointer <=#Tp 0;
|
TxPointer <=#Tp 0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointer <=#Tp ram_do;
|
TxPointer <=#Tp ram_do;
|
else
|
else
|
if(MasterWbTX & ~BlockingIncrementTxPointer)
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
if(TxWordAcc)
|
|
TxPointer <=#Tp TxPointer + 3'h4; // Word access
|
TxPointer <=#Tp TxPointer + 3'h4; // Word access
|
else if(TxHalfAcc)
|
|
TxPointer <=#Tp TxPointer + 2'h2; // Half access
|
|
else
|
|
TxPointer <=#Tp TxPointer + 1'h1; // Byte access
|
|
end
|
end
|
|
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLatched[1:0] <=#Tp 0;
|
TxPointerLatched[1:0] <=#Tp 0;
|
| Line 768... |
Line 758... |
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerLatched[1:0] <=#Tp ram_do[1:0];
|
TxPointerLatched[1:0] <=#Tp ram_do[1:0];
|
end
|
end
|
|
|
|
|
assign TxBurstAcc = ~TxPointer[3] & ~TxPointer[2] & ~TxPointer[1] & ~TxPointer[0]; // Add a counter that count burst to 4
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
assign TxWordAcc = ~TxPointer[1] & ~TxPointer[0];
|
always @ (posedge WB_CLK_I or posedge Reset)
|
assign TxHalfAcc = TxPointer[1] & ~TxPointer[0];
|
begin
|
assign TxByteAcc = TxPointer[0];
|
if(Reset)
|
|
TxPointerLatched_rst[1:0] <=#Tp 0;
|
wire [3:0] m_wb_sel_tmp_tx;
|
else
|
reg [3:0] m_wb_sel_tmp_rx;
|
if(TxEn & TxEn_q & TxPointerRead)
|
|
TxPointerLatched_rst[1:0] <=#Tp ram_do[1:0];
|
|
else
|
assign m_wb_sel_tmp_tx[0] = TxWordAcc | TxHalfAcc | TxByteAcc & TxPointer[1];
|
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
|
assign m_wb_sel_tmp_tx[1] = TxWordAcc | TxHalfAcc;
|
TxPointerLatched_rst[1:0] <=#Tp 0;
|
assign m_wb_sel_tmp_tx[2] = TxWordAcc | TxByteAcc & ~TxPointer[1];
|
end
|
assign m_wb_sel_tmp_tx[3] = TxWordAcc;
|
|
|
|
|
|
|
reg [3:0] m_wb_sel_tmp_rx;
|
wire MasterAccessFinished;
|
wire MasterAccessFinished;
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 794... |
Line 784... |
BlockingIncrementTxPointer <=#Tp 0;
|
BlockingIncrementTxPointer <=#Tp 0;
|
else
|
else
|
if(MasterAccessFinished)
|
if(MasterAccessFinished)
|
BlockingIncrementTxPointer <=#Tp 0;
|
BlockingIncrementTxPointer <=#Tp 0;
|
else
|
else
|
if(MasterWbTX)
|
if(IncrTxPointer)
|
BlockingIncrementTxPointer <=#Tp 1'b1;
|
BlockingIncrementTxPointer <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
wire TxBufferAlmostFull;
|
wire TxBufferAlmostFull;
|
| Line 842... |
Line 832... |
end
|
end
|
|
|
|
|
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
reg cyc_cleared;
|
reg [3:0] state;
|
|
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
|
state <=#Tp 4'h0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'h0;
|
m_wb_sel_o <=#Tp 4'h0;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared}) // synopsys parallel_case
|
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared}) // synopsys parallel_case
|
6'b00_01_0_x, 6'b00_11_0_x :
|
6'b00_01_0_x, 6'b00_11_0_x :
|
begin
|
begin
|
|
state <=#Tp 4'h1;
|
MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b00_10_0_x, 6'b00_10_1_x :
|
6'b00_10_0_x, 6'b00_10_1_x :
|
begin
|
begin
|
|
state <=#Tp 4'h2;
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_adr_o <=#Tp {TxPointer[31:2], 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
|
m_wb_sel_o <=#Tp 4'hf;
|
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
6'b10_10_0_1 :
|
6'b10_10_0_1 :
|
begin
|
begin
|
|
state <=#Tp 4'h3;
|
MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_adr_o <=#Tp {TxPointer[31:2], 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
|
m_wb_sel_o <=#Tp 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
6'b01_01_0_1 :
|
6'b01_01_0_1 :
|
begin
|
begin
|
|
state <=#Tp 4'h4;
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b10_01_0_1, 6'b10_11_0_1 :
|
6'b10_01_0_1, 6'b10_11_0_1 :
|
begin
|
begin
|
|
state <=#Tp 4'h5;
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b01_10_0_1, 6'b01_11_0_1 :
|
6'b01_10_0_1, 6'b01_11_0_1 :
|
begin
|
begin
|
|
state <=#Tp 4'h6;
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_adr_o <=#Tp {TxPointer[31:2], 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
|
m_wb_sel_o <=#Tp 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
|
6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
|
begin
|
begin
|
|
state <=#Tp 4'h7;
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b1;
|
cyc_cleared<=#Tp 1'b1;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b10_00_1_x, 6'b01_00_1_x :
|
6'b10_00_1_x, 6'b01_00_1_x :
|
begin
|
begin
|
|
state <=#Tp 4'h8;
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b10_00_0_1, 6'b01_00_0_1 :
|
6'b10_00_0_1, 6'b01_00_0_1 :
|
begin
|
begin
|
|
state <=#Tp 4'h9;
|
MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
|
MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
default: // Don't touch
|
default: // Don't touch
|
begin
|
begin
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbRX <=#Tp MasterWbRX;
|
MasterWbRX <=#Tp MasterWbRX;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
m_wb_sel_o <=#Tp m_wb_sel_o;
|
m_wb_sel_o <=#Tp m_wb_sel_o;
|
|
IncrTxPointer<=#Tp IncrTxPointer;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
wire TxFifoClear;
|
wire TxFifoClear;
|
wire [31:0] tx_fifo_dat_i;
|
|
|
|
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
|
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
|
|
wire [4:0] txfifo_cnt;
|
reg [23:16] LatchedData;
|
|
wire [23:16] TempData;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedData[23:16] <=#Tp 0;
|
|
else
|
|
if(MasterWbTX & m_wb_ack_i & m_wb_sel_o[2])
|
|
LatchedData[23:16] <=#Tp m_wb_dat_i[23:16];
|
|
end
|
|
|
|
assign TempData[23:16] = m_wb_sel_o[2]? m_wb_dat_i[23:16] : LatchedData[23:16];
|
|
|
|
assign tx_fifo_dat_i[31:0] = {m_wb_dat_i[31:24], TempData[23:16], m_wb_dat_i[15:8], m_wb_dat_i[7:0]};
|
|
|
|
|
|
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
|
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
|
tx_fifo ( .data_in(tx_fifo_dat_i), .data_out(TxData_wb),
|
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(MasterWbTX & m_wb_ack_i & m_wb_sel_o[0]), .read(ReadTxDataFromFifo_wb),
|
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
|
.clear(TxFifoClear), .full(TxBufferFull),
|
.clear(TxFifoClear), .full(TxBufferFull),
|
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
|
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
|
.empty(TxBufferEmpty), .cnt()
|
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
|
);
|
);
|
|
|
|
|
reg StartOccured;
|
reg StartOccured;
|
reg TxStartFrm_sync1;
|
reg TxStartFrm_sync1;
|
| Line 1182... |
Line 1174... |
assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
|
assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
|
assign TxDonePulse_q = TxDone_wb_q & ~TxDone_wb_q2;
|
assign TxDonePulse_q = TxDone_wb_q & ~TxDone_wb_q2;
|
assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
|
assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
|
|
|
|
|
assign TPauseRq = 0;
|
|
assign TxPauseTV[15:0] = TxLength[15:0];
|
|
|
|
|
|
// Generating delayed signals
|
// Generating delayed signals
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1361... |
Line 1350... |
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
TxByteCnt <=#Tp TxByteCnt + 1'b1;
|
TxByteCnt <=#Tp TxByteCnt + 1'b1;
|
end
|
end
|
|
|
|
/*
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
reg ReadTxDataFromFifo_sync1;
|
|
reg ReadTxDataFromFifo_sync2;
|
|
reg ReadTxDataFromFifo_sync3;
|
|
reg ReadTxDataFromFifo_syncb1;
|
|
reg ReadTxDataFromFifo_syncb2;
|
|
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
|
else
|
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
|
else
|
|
if(ReadTxDataFromFifo_syncb2)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
|
end
|
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
|
|
end
|
|
|
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
|
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
*/
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
reg ReadTxDataFromFifo_sync1;
|
reg ReadTxDataFromFifo_sync1;
|
reg ReadTxDataFromFifo_sync2;
|
reg ReadTxDataFromFifo_sync2;
|
reg ReadTxDataFromFifo_sync3;
|
reg ReadTxDataFromFifo_sync3;
|
reg ReadTxDataFromFifo_syncb1;
|
reg ReadTxDataFromFifo_syncb1;
|
reg ReadTxDataFromFifo_syncb2;
|
reg ReadTxDataFromFifo_syncb2;
|
|
reg ReadTxDataFromFifo_syncb3;
|
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
else
|
else
|
if(ReadTxDataFromFifo_syncb2)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
|
else
|
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
|
else
|
|
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
end
|
end
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
// Synchronizing TxStartFrm_wb to MTxClk
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 1415... |
Line 1470... |
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
|
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
|
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
|
end
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
|
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
|
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
|
else
|
else
|
| Line 1480... |
Line 1543... |
else
|
else
|
TxAbort_wb <=#Tp TxAbortSync1;
|
TxAbort_wb <=#Tp TxAbortSync1;
|
end
|
end
|
|
|
|
|
assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
|
reg RxAbortSync1;
|
|
reg RxAbortSync2;
|
|
reg RxAbortSync3;
|
|
reg RxAbortSync4;
|
|
reg RxAbortSyncb1;
|
|
reg RxAbortSyncb2;
|
|
|
|
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
|
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
|
|
|
// Reading the Rx buffer descriptor
|
// Reading the Rx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1505... |
Line 1576... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDReady <=#Tp 1'b0;
|
RxBDReady <=#Tp 1'b0;
|
else
|
else
|
|
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
|
|
RxBDReady <=#Tp 1'b0;
|
|
else
|
if(RxEn & RxEn_q & RxBDRead)
|
if(RxEn & RxEn_q & RxBDRead)
|
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
|
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
|
else
|
|
if(ShiftEnded | RxAbort)
|
|
RxBDReady <=#Tp 1'b0;
|
|
end
|
end
|
|
|
// Latching Rx buffer descriptor status
|
// Latching Rx buffer descriptor status
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 1763... |
Line 1834... |
end
|
end
|
|
|
|
|
reg WriteRxDataToFifoSync1;
|
reg WriteRxDataToFifoSync1;
|
reg WriteRxDataToFifoSync2;
|
reg WriteRxDataToFifoSync2;
|
|
reg WriteRxDataToFifoSync3;
|
|
|
|
|
// Indicating start of the reception process
|
// Indicating start of the reception process
|
//assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
//assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLatched)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLatched)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
/*
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifo <=#Tp 1'b0;
|
|
else
|
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
|
WriteRxDataToFifo <=#Tp 1'b1;
|
|
else
|
|
if(WriteRxDataToFifoSync1 | RxAbort)
|
|
WriteRxDataToFifo <=#Tp 1'b0;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync1 <=#Tp 1'b0;
|
|
else
|
|
if(WriteRxDataToFifo)
|
|
WriteRxDataToFifoSync1 <=#Tp 1'b1;
|
|
else
|
|
WriteRxDataToFifoSync1 <=#Tp 1'b0;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync2 <=#Tp 1'b0;
|
|
else
|
|
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
|
|
end
|
|
|
|
wire WriteRxDataToFifo_wb;
|
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
|
|
*/
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifo <=#Tp 1'b0;
|
WriteRxDataToFifo <=#Tp 1'b0;
|
else
|
else
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
WriteRxDataToFifo <=#Tp 1'b1;
|
WriteRxDataToFifo <=#Tp 1'b1;
|
else
|
else
|
if(WriteRxDataToFifoSync1 | RxAbort)
|
if(WriteRxDataToFifoSync2 | RxAbort)
|
WriteRxDataToFifo <=#Tp 1'b0;
|
WriteRxDataToFifo <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
| Line 1802... |
Line 1911... |
WriteRxDataToFifoSync2 <=#Tp 1'b0;
|
WriteRxDataToFifoSync2 <=#Tp 1'b0;
|
else
|
else
|
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
|
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
|
end
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync3 <=#Tp 1'b0;
|
|
else
|
|
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
|
|
end
|
|
|
wire WriteRxDataToFifo_wb;
|
wire WriteRxDataToFifo_wb;
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
|
|
|
reg RxAbortSync1;
|
|
reg RxAbortSync2;
|
|
reg RxAbortSyncb1;
|
|
reg RxAbortSyncb2;
|
|
|
|
reg LatchedRxStartFrm;
|
reg LatchedRxStartFrm;
|
reg SyncRxStartFrm;
|
reg SyncRxStartFrm;
|
reg SyncRxStartFrm_q;
|
reg SyncRxStartFrm_q;
|
|
reg SyncRxStartFrm_q2;
|
wire RxFifoReset;
|
wire RxFifoReset;
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedRxStartFrm <=#Tp 0;
|
LatchedRxStartFrm <=#Tp 0;
|
else
|
else
|
if(RxStartFrm & ~SyncRxStartFrm)
|
if(RxStartFrm & ~SyncRxStartFrm_q)
|
LatchedRxStartFrm <=#Tp 1;
|
LatchedRxStartFrm <=#Tp 1;
|
else
|
else
|
if(SyncRxStartFrm)
|
if(SyncRxStartFrm_q)
|
LatchedRxStartFrm <=#Tp 0;
|
LatchedRxStartFrm <=#Tp 0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
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| Line 1848... |
Line 1962... |
SyncRxStartFrm_q <=#Tp 0;
|
SyncRxStartFrm_q <=#Tp 0;
|
else
|
else
|
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
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SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
|
end
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
SyncRxStartFrm_q2 <=#Tp 0;
|
|
else
|
|
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
|
|
end
|
|
|
|
|
assign RxFifoReset = SyncRxStartFrm & ~SyncRxStartFrm_q;
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assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
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|
|
|
wire [4:0] rxfifo_cnt;
|
|
|
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
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eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.empty(RxBufferEmpty), .cnt()
|
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
|
);
|
);
|
|
|
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
|
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
|
|
|
|
|
| Line 1954... |
Line 2077... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync1 <=#Tp 1'b0;
|
RxAbortSync1 <=#Tp 1'b0;
|
else
|
else
|
RxAbortSync1 <=#Tp RxAbort;
|
// RxAbortSync1 <=#Tp RxAbort;
|
|
RxAbortSync1 <=#Tp RxAbortLatched;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync2 <=#Tp 1'b0;
|
RxAbortSync2 <=#Tp 1'b0;
|
else
|
else
|
RxAbortSync2 <=#Tp RxAbortSync1;
|
RxAbortSync2 <=#Tp RxAbortSync1;
|
end
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSync3 <=#Tp 1'b0;
|
|
else
|
|
RxAbortSync3 <=#Tp RxAbortSync2;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxAbortSync4 <=#Tp 1'b0;
|
|
else
|
|
RxAbortSync4 <=#Tp RxAbortSync3;
|
|
end
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSyncb1 <=#Tp 1'b0;
|
RxAbortSyncb1 <=#Tp 1'b0;
|
else
|
else
|
| Line 1987... |
Line 2127... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortLatched <=#Tp 1'b0;
|
RxAbortLatched <=#Tp 1'b0;
|
else
|
else
|
|
if(RxAbortSyncb2)
|
|
RxAbortLatched <=#Tp 1'b0;
|
|
else
|
if(RxAbort)
|
if(RxAbort)
|
RxAbortLatched <=#Tp 1'b1;
|
RxAbortLatched <=#Tp 1'b1;
|
else
|
|
if(RxStartFrm)
|
|
RxAbortLatched <=#Tp 1'b0;
|
|
end
|
end
|
|
|
|
/*
|
|
reg LoadStatusBlocked;
|
|
|
reg LoadStatusBlocked;
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
always @ (posedge MRxClk or posedge Reset)
|
if(Reset)
|
begin
|
LoadStatusBlocked <=#Tp 1'b0;
|
if(Reset)
|
else
|
LoadStatusBlocked <=#Tp 1'b0;
|
if(LoadRxStatus & ~RxAbortLatched)
|
else
|
LoadStatusBlocked <=#Tp 1'b1;
|
if(LoadRxStatus & ~RxAbortLatched)
|
else
|
LoadStatusBlocked <=#Tp 1'b1;
|
if(RxStatusWrite_rck | RxStartFrm)
|
else
|
LoadStatusBlocked <=#Tp 1'b0;
|
if(RxStatusWrite_rck | RxStartFrm)
|
end
|
LoadStatusBlocked <=#Tp 1'b0;
|
*/
|
end
|
|
|
|
// LatchedRxLength[15:0]
|
// LatchedRxLength[15:0]
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedRxLength[15:0] <=#Tp 16'h0;
|
LatchedRxLength[15:0] <=#Tp 16'h0;
|
else
|
else
|
if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
|
// if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
|
|
if(LoadRxStatus)
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
end
|
end
|
|
|
|
|
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
| Line 2027... |
Line 2168... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusInLatched <=#Tp 'h0;
|
RxStatusInLatched <=#Tp 'h0;
|
else
|
else
|
if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
|
// if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
|
|
if(LoadRxStatus)
|
RxStatusInLatched <=#Tp RxStatusIn;
|
RxStatusInLatched <=#Tp RxStatusIn;
|
end
|
end
|
|
|
|
|
// Rx overrun
|
// Rx overrun
|
| Line 2105... |
Line 2247... |
else
|
else
|
RxE_IRQ <=#Tp 1'b0;
|
RxE_IRQ <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
assign RxC_IRQ = 1'b0;
|
|
assign TxC_IRQ = 1'b0;
|
|
assign Busy_IRQ = 1'b0;
|
assign Busy_IRQ = 1'b0;
|
|
|
|
|
|
|
|
|
| Line 2147... |
Line 2287... |
// bit 3 od rx je ReceivedPacketTooBig
|
// bit 3 od rx je ReceivedPacketTooBig
|
// bit 2 od rx je ShortFrame
|
// bit 2 od rx je ShortFrame
|
// bit 1 od rx je LatchedCrcError
|
// bit 1 od rx je LatchedCrcError
|
// bit 0 od rx je RxLateCollision
|
// bit 0 od rx je RxLateCollision
|
|
|
|
assign reg1 = RxPointer[31:0]; /* 0x58 */
|
|
|
|
assign reg2 = { /* 0x5c */
|
|
RxStatusWriteLatched, // 31
|
|
RxStatusWrite_rck, // 30
|
|
RxEn_needed, // 29
|
|
StartRxBDRead, // 28
|
|
RxStatusWrite, // 27
|
|
1'b1, //RxAbortLatched, // 26
|
|
RxBDRead, // 25
|
|
RxBDReady, // 24
|
|
ShiftEnded, // 23
|
|
RxPointerRead, // 23
|
|
LastByteIn, // 21
|
|
ShiftWillEnd, // 20
|
|
2'h0, RxByteCnt[1:0], // 19:16
|
|
2'h0, RxPointerLatched[1:0], // 15:12
|
|
RxBDAddress[7:0], // 11:4
|
|
state[3:0] // 3:0
|
|
};
|
|
|
|
assign reg3 = { /* 0x60 */
|
|
ShiftEndedSync_c2, // 31
|
|
RxAbortSyncb1, // 30
|
|
RxAbortSyncb2, // 31
|
|
RxAbortSync1, // 30
|
|
RxAbortSync2, // 29
|
|
1'b0, //LoadStatusBlocked, // 28
|
|
LoadRxStatus, // 27
|
|
1'b0, //LoadStatusBlocked, // 26
|
|
RxOverrun, // 25
|
|
RxAbort, // 24
|
|
RxValid, // 23
|
|
RxEndFrm, // 22
|
|
RxEnableWindow, // 21
|
|
StartShiftWillEnd, // 20
|
|
ShiftWillEnd, // 19
|
|
ShiftEnded_tck, // 18
|
|
SetWriteRxDataToFifo, // 17
|
|
WriteRxDataToFifo, // 16
|
|
WriteRxDataToFifoSync3, // 15
|
|
WriteRxDataToFifoSync2, // 14
|
|
WriteRxDataToFifoSync1, // 13
|
|
WriteRxDataToFifo_wb, // 12
|
|
LatchedRxStartFrm, // 11
|
|
RxStartFrm, // 10
|
|
SyncRxStartFrm, // 9
|
|
SyncRxStartFrm_q, // 8
|
|
SyncRxStartFrm_q2, // 7
|
|
RxBufferEmpty, // 6
|
|
RxBufferFull, // 5
|
|
rxfifo_cnt[4:0] // 4:0
|
|
};
|
|
|
|
assign reg4 = { /* 0x64 */
|
|
WriteRxDataToMemory, // 4
|
|
ShiftEndedSync1, // 3
|
|
ShiftEndedSync2, // 2
|
|
ShiftEndedSync3, // 1
|
|
ShiftEndedSync_c1 // 0
|
|
};
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
