| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2002/03/09 13:51:20 mohor
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// Status was not latched correctly sometimes. Fixed.
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//
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// Revision 1.15 2002/03/08 06:56:46 mohor
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// Revision 1.15 2002/03/08 06:56:46 mohor
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// Big Endian problem when sending frames fixed.
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// Big Endian problem when sending frames fixed.
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//
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//
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// Revision 1.14 2002/03/02 19:12:40 mohor
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// Revision 1.14 2002/03/02 19:12:40 mohor
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// Byte ordering changed (Big Endian used). casex changed with case because
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// Byte ordering changed (Big Endian used). casex changed with case because
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| Line 1624... |
Line 1627... |
reg RxAbortSyncb1;
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reg RxAbortSyncb1;
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reg RxAbortSyncb2;
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reg RxAbortSyncb2;
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eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
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eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
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rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), .clk(WB_CLK_I),
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rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
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.reset(Reset), .write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
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.clk(WB_CLK_I), .reset(Reset),
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.clear(RxAbortSync2), .full(RxBufferFull), .almost_full(RxBufferAlmostFull),
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.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
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.almost_empty(RxBufferAlmostEmpty), .empty(RxBufferEmpty));
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.clear(RxAbortSync2 | RxStatusWriteLatched), .full(RxBufferFull),
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.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
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.empty(RxBufferEmpty)
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);
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assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
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assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
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