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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2002/10/24 18:53:03 mohor
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// fpga define added.
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//
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// Revision 1.3 2002/10/11 16:57:54 igorm
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// Revision 1.3 2002/10/11 16:57:54 igorm
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// eth_defines.v tagged with rel_5 used.
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// eth_defines.v tagged with rel_5 used.
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//
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//
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// Revision 1.25 2002/10/10 16:47:44 mohor
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// Revision 1.25 2002/10/10 16:47:44 mohor
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// Defines changed to have ETH_ prolog.
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// Defines changed to have ETH_ prolog.
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//
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//
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//
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//
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//
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//
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//
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//
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`ifdef fpga
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`define FPGA
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`else
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`endif
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//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
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//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
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`ifdef FPGA
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// Ethernet implemented in Xilinx Chips
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`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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`define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
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// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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`else
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`define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
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// Ethernet implemented in ASIC with Virtual Silicon RAMs
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`endif
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// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGT_ADR 8'h3 // 0xC
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