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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_miim.v] - Diff between revs 133 and 284

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Rev 133 Rev 284
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.4  2002/08/14 18:32:10  mohor
 
// - Busy signal was not set on time when scan status operation was performed
 
// and clock was divided with more than 2.
 
// - Nvalid remains valid two more clocks (was previously cleared too soon).
 
//
// Revision 1.3  2002/01/23 10:28:16  mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
//
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
Line 344... Line 349...
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
 
 
// Busy
// Busy
assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
 
 
 
 
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)

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