| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.23 2002/11/19 18:13:49 mohor
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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//
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// r_Rst signal does not reset any module any more and is removed from the design.
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// r_Rst signal does not reset any module any more and is removed from the design.
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//
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//
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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// Ethernet debug registers removed.
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| Line 151... |
Line 154... |
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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StartTxDone, TxClk, RxClk, ReceivedPauseFrm
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StartTxDone, TxClk, RxClk, SetPauseTimer
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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| Line 242... |
Line 245... |
input RstTxPauseRq;
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input RstTxPauseRq;
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input TxCtrlEndFrm;
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input TxCtrlEndFrm;
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input StartTxDone;
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input StartTxDone;
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input TxClk;
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input TxClk;
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input RxClk;
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input RxClk;
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input ReceivedPauseFrm; // sinhroniziraj tale shit da bo delal interrupt. Pazi na PassAll bit
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input SetPauseTimer;
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reg irq_txb;
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reg irq_txb;
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reg irq_txe;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxb;
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reg irq_rxe;
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reg irq_rxe;
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| Line 260... |
Line 263... |
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
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reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
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reg SetRxCIrq_rxclk;
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reg SetRxCIrq_rxclk;
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reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
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reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
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reg SetRxCIrq;
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reg SetRxCIrq;
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reg ResetRxCIrq_sync1, ResetRxCIrq_sync2;
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reg ResetRxCIrq_sync1;
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reg ResetRxCIrq_sync2;
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reg ResetRxCIrq_sync3;
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wire Write = Cs & Rw;
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wire Write = Cs & Rw;
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wire Read = Cs & ~Rw;
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wire Read = Cs & ~Rw;
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
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| Line 779... |
Line 784... |
always @ (posedge RxClk or posedge Reset)
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always @ (posedge RxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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SetRxCIrq_rxclk <=#Tp 1'b0;
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SetRxCIrq_rxclk <=#Tp 1'b0;
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else
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else
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if(ReceivedPauseFrm & r_RxFlow)
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if(SetPauseTimer & r_RxFlow)
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SetRxCIrq_rxclk <=#Tp 1'b1;
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SetRxCIrq_rxclk <=#Tp 1'b1;
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else
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else
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if(ResetRxCIrq_sync2)
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if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
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SetRxCIrq_rxclk <=#Tp 1'b0;
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SetRxCIrq_rxclk <=#Tp 1'b0;
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end
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end
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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| Line 827... |
Line 832... |
ResetRxCIrq_sync1 <=#Tp 1'b0;
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ResetRxCIrq_sync1 <=#Tp 1'b0;
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else
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else
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ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
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ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
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end
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end
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always @ (posedge TxClk or posedge Reset)
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always @ (posedge RxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ResetRxCIrq_sync2 <=#Tp 1'b0;
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ResetRxCIrq_sync2 <=#Tp 1'b0;
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else
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else
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ResetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
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ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
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end
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end
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always @ (posedge RxClk or posedge Reset)
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begin
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if(Reset)
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ResetRxCIrq_sync3 <=#Tp 1'b0;
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else
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ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
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end
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// Interrupt generation
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// Interrupt generation
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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