| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.27 2002/07/25 18:15:37 mohor
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|
// RxAbort changed. Packets received with MRxErr (from PHY) are also
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|
// aborted.
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//
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// Revision 1.26 2002/07/17 18:51:50 mohor
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// Revision 1.26 2002/07/17 18:51:50 mohor
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// EXTERNAL_DMA removed. External DMA not supported.
|
// EXTERNAL_DMA removed. External DMA not supported.
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//
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//
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// Revision 1.25 2002/05/03 10:15:50 mohor
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// Revision 1.25 2002/05/03 10:15:50 mohor
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// Outputs registered. Reset changed for eth_wishbone module.
|
// Outputs registered. Reset changed for eth_wishbone module.
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| Line 259... |
Line 263... |
wire TxUnderRun;
|
wire TxUnderRun;
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wire TxDone;
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wire TxDone;
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wire [5:0] CollValid;
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wire [5:0] CollValid;
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|
|
|
|
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reg WillSendControlFrame_sync1;
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reg WillSendControlFrame_sync2;
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reg WillSendControlFrame_sync3;
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reg RstTxPauseRq;
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|
|
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// Connecting Miim module
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// Connecting Miim module
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eth_miim miim1
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eth_miim miim1
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(
|
(
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| Line 305... |
Line 313... |
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
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wire [7:0] r_TxBDNum; // Receive buffer descriptor number
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wire [6:0] r_IPGT; //
|
wire [6:0] r_IPGT; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR2; //
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wire [6:0] r_IPGR2; //
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wire [5:0] r_CollValid; //
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wire [5:0] r_CollValid; //
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wire r_TPauseRq; // Transmit PAUSE request pulse
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wire [15:0] r_TxPauseTV; // Transmit PAUSE value
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wire r_TxPauseRq; // Transmit PAUSE request
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|
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wire [3:0] r_MaxRet; //
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wire [3:0] r_MaxRet; //
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wire r_NoBckof; //
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wire r_NoBckof; //
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wire r_ExDfrEn; //
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wire r_ExDfrEn; //
|
wire TX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
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wire TX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
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wire TPauseRq; // Sinhronized Tx PAUSE request
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire r_TxFlow; // Tx flow control enable
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wire r_TxFlow; // Tx flow control enable
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxE_IRQ; // Interrupt Tx Error
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wire TxE_IRQ; // Interrupt Tx Error
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxE_IRQ; // Interrupt Rx Error
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wire RxE_IRQ; // Interrupt Rx Error
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire TxC_IRQ; // Interrupt Tx Control Frame
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wire RxC_IRQ; // Interrupt Rx Control Frame
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|
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wire DWord;
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wire DWord;
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wire BDAck;
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wire BDAck;
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire BDCs; // Buffer descriptor CS
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wire BDCs; // Buffer descriptor CS
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| Line 376... |
Line 381... |
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
|
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
|
end
|
end
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end
|
end
|
`endif
|
`endif
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|
|
|
wire [31:0] reg1, reg2, reg3, reg4;
|
|
|
// Connecting Ethernet registers
|
// Connecting Ethernet registers
|
eth_registers ethreg1
|
eth_registers ethreg1
|
(
|
(
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
| Line 391... |
Line 396... |
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
|
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
|
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.TxC_IRQ(TxC_IRQ), .RxC_IRQ(RxC_IRQ), .r_IPGT(r_IPGT),
|
.r_IPGT(r_IPGT),
|
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
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.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
|
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
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.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
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.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
|
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
|
.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
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.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
|
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
|
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
|
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
|
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
|
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
|
.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o),
|
.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o),
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.r_HASH0(r_HASH0), .r_HASH1(r_HASH1)
|
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
|
|
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
|
|
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
|
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.ReceivedPauseFrm(ReceivedPauseFrm),
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|
|
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.reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4)
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|
|
);
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);
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|
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|
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wire [7:0] RxData;
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wire [7:0] RxData;
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| Line 417... |
Line 428... |
|
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wire WillTransmit; // Will transmit (to RxEthMAC)
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wire WillTransmit; // Will transmit (to RxEthMAC)
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wire ResetCollision; // Reset Collision (for synchronizing collision)
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wire ResetCollision; // Reset Collision (for synchronizing collision)
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wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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wire WillSendControlFrame;
|
wire WillSendControlFrame;
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wire TxCtrlEndFrm;
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wire ReceivedPauseFrm;
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wire ReceiveEnd;
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wire ReceiveEnd;
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wire ReceivedPacketGood;
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wire ReceivedPacketGood;
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wire ReceivedLengthOK;
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wire ReceivedLengthOK;
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wire InvalidSymbol;
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wire InvalidSymbol;
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wire LatchedCrcError;
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wire LatchedCrcError;
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wire RxLateCollision;
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wire RxLateCollision;
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wire [3:0] RetryCntLatched;
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wire [3:0] RetryCntLatched;
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wire [3:0] RetryCnt;
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wire [3:0] RetryCnt;
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wire StartTxDone;
|
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wire StartTxAbort;
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wire StartTxAbort;
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wire MaxCollisionOccured;
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wire MaxCollisionOccured;
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wire RetryLimit;
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wire RetryLimit;
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wire StatePreamble;
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wire StatePreamble;
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wire [1:0] StateData;
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wire [1:0] StateData;
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|
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// Connecting MACControl
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// Connecting MACControl
|
eth_maccontrol maccontrol1
|
eth_maccontrol maccontrol1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(r_TxPauseRq),
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.TxPauseTV(TxPauseTV), .TxDataIn(TxData),
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.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
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.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
|
.RxData(RxData), .RxValid(RxValid),
|
.RxData(RxData), .RxValid(RxValid),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
| Line 620... |
Line 628... |
RxEnSync <= #Tp r_RxEn;
|
RxEnSync <= #Tp r_RxEn;
|
end
|
end
|
|
|
|
|
|
|
|
// Synchronizing WillSendControlFrame to WB_CLK;
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
|
if(wb_rst_i)
|
|
WillSendControlFrame_sync1 <= 1'b0;
|
|
else
|
|
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
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|
end
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|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
|
if(wb_rst_i)
|
|
WillSendControlFrame_sync2 <= 1'b0;
|
|
else
|
|
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
|
|
end
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
|
if(wb_rst_i)
|
|
WillSendControlFrame_sync3 <= 1'b0;
|
|
else
|
|
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
|
|
end
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
|
if(wb_rst_i)
|
|
RstTxPauseRq <= 1'b0;
|
|
else
|
|
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
|
|
end
|
|
|
|
|
// Connecting Wishbone module
|
// Connecting Wishbone module
|
eth_wishbone wishbone
|
eth_wishbone wishbone
|
(
|
(
|
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
|
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
|
| Line 642... |
Line 683... |
|
|
//TX
|
//TX
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.TxUsedData(TxUsedData), .TxData(TxData),
|
.TxUsedData(TxUsedData), .TxData(TxData),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
|
.TxDone(TxDone),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
|
|
|
// Register
|
// Register
|
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
|
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
|
.TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RecSmall(r_RecSmall),
|
.TX_BD_NUM_Wr(TX_BD_NUM_Wr),
|
|
|
//RX
|
//RX
|
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
|
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
|
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
|
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), .TxC_IRQ(TxC_IRQ),
|
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.RxC_IRQ(RxC_IRQ),
|
|
|
|
.RxAbort(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol),
|
.RxAbort(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | ReceivedPauseFrm & ~r_PassAll),
|
|
|
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
|
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
|
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
|
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
|
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
|
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
|
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
|
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
|
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)
|
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),
|
|
|
|
|
|
.reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4)
|
|
|
);
|
);
|
|
|
|
|
|
|
| Line 691... |
Line 730... |
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
|
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
|
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
|
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
|
.LateCollLatched(LateCollLatched), .StartDefer(StartDefer), .DeferLatched(DeferLatched),
|
.LateCollLatched(LateCollLatched), .StartDefer(StartDefer), .DeferLatched(DeferLatched),
|
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
|
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
|
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
|
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
|
.LatchedMRxErr(LatchedMRxErr)
|
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
