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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2002/09/12 14:50:17 mohor
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// CarrierSenseLost bug fixed when operating in full duplex mode.
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//
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// Revision 1.30 2002/09/10 10:35:23 mohor
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// Revision 1.30 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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// Ethernet debug registers removed.
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//
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//
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// Revision 1.29 2002/09/09 13:03:13 mohor
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// Revision 1.29 2002/09/09 13:03:13 mohor
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// Error acknowledge is generated when accessing BDs and RST bit in the
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// Error acknowledge is generated when accessing BDs and RST bit in the
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Line 347... |
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wire DWord;
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wire DWord;
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wire BDAck;
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wire BDAck;
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire BDCs; // Buffer descriptor CS
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wire BDCs; // Buffer descriptor CS
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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// but data is not valid.
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wire temp_wb_ack_o;
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wire temp_wb_ack_o;
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wire [31:0] temp_wb_dat_o;
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wire [31:0] temp_wb_dat_o;
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wire temp_wb_err_o;
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wire temp_wb_err_o;
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Line 363... |
`endif
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`endif
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assign DWord = &wb_sel_i;
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assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst);
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst | CsMiss);
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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