| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
|
//
|
// CVS Revision History
|
// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.33 2002/10/10 16:29:30 mohor
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// BIST added.
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//
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// Revision 1.32 2002/09/20 17:12:58 mohor
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// Revision 1.32 2002/09/20 17:12:58 mohor
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// CsMiss added. When address between 0x800 and 0xfff is accessed within
|
// CsMiss added. When address between 0x800 and 0xfff is accessed within
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// Ethernet Core, error acknowledge is generated.
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// Ethernet Core, error acknowledge is generated.
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//
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//
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// Revision 1.31 2002/09/12 14:50:17 mohor
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// Revision 1.31 2002/09/12 14:50:17 mohor
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| Line 184... |
Line 187... |
// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
|
|
|
|
`ifdef ETH_WISHBONE_B3
|
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m_wb_cti_o, m_wb_bte_o,
|
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`endif
|
|
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//TX
|
//TX
|
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
|
|
|
//RX
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//RX
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
|
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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| Line 232... |
Line 239... |
output m_wb_cyc_o;
|
output m_wb_cyc_o;
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output m_wb_stb_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
|
input m_wb_ack_i;
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input m_wb_err_i;
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input m_wb_err_i;
|
|
|
|
`ifdef ETH_WISHBONE_B3
|
|
output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [1:0] m_wb_bte_o; // Burst Type Extension
|
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`endif
|
|
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// Tx
|
// Tx
|
input mtx_clk_pad_i; // Transmit clock (from PHY)
|
input mtx_clk_pad_i; // Transmit clock (from PHY)
|
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
|
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
|
output mtxen_pad_o; // Transmit enable (to PHY)
|
output mtxen_pad_o; // Transmit enable (to PHY)
|
| Line 709... |
Line 720... |
// WISHBONE master
|
// WISHBONE master
|
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
|
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
|
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
|
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
|
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
|
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
|
|
|
|
`ifdef ETH_WISHBONE_B3
|
|
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
|
|
`endif
|
|
|
|
|
//TX
|
//TX
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.TxUsedData(TxUsedData), .TxData(TxData),
|
.TxUsedData(TxUsedData), .TxData(TxData),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxDone(TxDone),
|
.TxDone(TxDone),
|
