URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 218 and 227

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Rev 218	Rev 227
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.35 2002/10/11 13:36:58 mohor`
	`// Typo error fixed. (When using Bist)`
	`//`
`// Revision 1.34 2002/10/10 16:49:50 mohor`	`// Revision 1.34 2002/10/10 16:49:50 mohor`
`// Signals for WISHBONE B3 compliant interface added.`	`// Signals for WISHBONE B3 compliant interface added.`
`//`	`//`
`// Revision 1.33 2002/10/10 16:29:30 mohor`	`// Revision 1.33 2002/10/10 16:29:30 mohor`
`// BIST added.`	`// BIST added.`
Line 207...	Line 210...

`int_o`	`int_o`

`// Bist`	`// Bist`
`ifdef ETH_BIST	`ifdef ETH_BIST
`, trst, SO, SI, shift_DR, capture_DR, extest, tck`	`,`
	`// debug chain signals`
	`scanb_rst, // bist scan reset`
	`scanb_clk, // bist scan clock`
	`scanb_si, // bist scan serial in`
	`scanb_so, // bist scan serial out`
	`scanb_en // bist scan shift enable`
`endif	`endif

`);`	`);`


Line 273...	Line 282...

`output int_o; // Interrupt output`	`output int_o; // Interrupt output`

`// Bist`	`// Bist`
`ifdef ETH_BIST	`ifdef ETH_BIST
`input trst;`	`input scanb_rst; // bist scan reset`
`input shift_DR, capture_DR, tck, extest;`	`input scanb_clk; // bist scan clock`
`input SI;`	`input scanb_si; // bist scan serial in`
`output SO;`	`output scanb_so; // bist scan serial out`
	`input scanb_en; // bist scan shift enable`
`endif	`endif

`wire [7:0] r_ClkDiv;`	`wire [7:0] r_ClkDiv;`
`wire r_MiiNoPre;`	`wire r_MiiNoPre;`
`wire [15:0] r_CtrlData;`	`wire [15:0] r_CtrlData;`
Line 755...	Line 765...
`.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),`	`.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),`
`.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)`	`.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)`

`ifdef ETH_BIST	`ifdef ETH_BIST
`,`	`,`
`.trst(trst), .SO(SO), .SI(SI),`	`.scanb_rst (scanb_rst),`
`.shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest),`	`.scanb_clk (scanb_clk),`
`.tck(tck)`	`.scanb_si (scanb_si),`
	`.scanb_so (scanb_so),`
	`.scanb_en (scanb_en)`
`endif	`endif
`);`	`);`

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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 218 and 227