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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.37 2002/11/13 22:25:36 tadejm
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// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
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//
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// Revision 1.36 2002/10/18 17:04:20 tadejm
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// Revision 1.36 2002/10/18 17:04:20 tadejm
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// Changed BIST scan signals.
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// Changed BIST scan signals.
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//
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//
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// Revision 1.35 2002/10/11 13:36:58 mohor
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// Revision 1.35 2002/10/11 13:36:58 mohor
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// Typo error fixed. (When using Bist)
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// Typo error fixed. (When using Bist)
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Line 347... |
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wire RegCs; // Connected to registers
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wire RegCs; // Connected to registers
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire r_RecSmall; // Receive small frames
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wire r_RecSmall; // Receive small frames
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wire r_Rst; // Reset
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wire r_LoopBck; // Loopback
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wire r_LoopBck; // Loopback
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wire r_TxEn; // Tx Enable
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wire r_TxEn; // Tx Enable
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wire r_RxEn; // Rx Enable
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wire r_RxEn; // Rx Enable
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wire MRxDV_Lb; // Muxed MII receive data valid
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wire MRxDV_Lb; // Muxed MII receive data valid
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Line 411... |
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
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assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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//assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst | CsMiss);
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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| Line 450... |
Line 451... |
(
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(
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.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
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.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
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.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
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.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
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.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
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.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
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.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
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.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
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.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
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.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
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.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
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.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
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.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
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.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
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.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
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.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
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.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
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.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
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.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
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.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
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