| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/01/23 10:28:16 mohor
|
|
// Link in the header changed.
|
|
//
|
// Revision 1.3 2001/10/19 08:43:51 mohor
|
// Revision 1.3 2001/10/19 08:43:51 mohor
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// simulation of the few cores in a one joined project.
|
// simulation of the few cores in a one joined project.
|
//
|
//
|
// Revision 1.2 2001/09/11 14:17:00 mohor
|
// Revision 1.2 2001/09/11 14:17:00 mohor
|
| Line 75... |
Line 78... |
|
|
|
|
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
|
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
|
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
|
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
|
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
|
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
|
ControlData, WillSendControlFrame
|
ControlData, WillSendControlFrame, BlockTxDone
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
|
|
| Line 101... |
Line 104... |
output TxCtrlEndFrm;
|
output TxCtrlEndFrm;
|
output SendingCtrlFrm;
|
output SendingCtrlFrm;
|
output CtrlMux;
|
output CtrlMux;
|
output [7:0] ControlData;
|
output [7:0] ControlData;
|
output WillSendControlFrame;
|
output WillSendControlFrame;
|
|
output BlockTxDone;
|
|
|
reg SendingCtrlFrm;
|
reg SendingCtrlFrm;
|
reg CtrlMux;
|
reg CtrlMux;
|
reg WillSendControlFrame;
|
reg WillSendControlFrame;
|
reg [3:0] DlyCrcCnt;
|
reg [3:0] DlyCrcCnt;
|
| Line 114... |
Line 118... |
reg TxCtrlStartFrm;
|
reg TxCtrlStartFrm;
|
reg TxCtrlStartFrm_q;
|
reg TxCtrlStartFrm_q;
|
reg TxCtrlEndFrm;
|
reg TxCtrlEndFrm;
|
reg [7:0] ControlData;
|
reg [7:0] ControlData;
|
reg TxUsedDataIn_q;
|
reg TxUsedDataIn_q;
|
|
reg BlockTxDone;
|
|
|
wire IncrementDlyCrcCnt;
|
wire IncrementDlyCrcCnt;
|
wire ResetByteCnt;
|
wire ResetByteCnt;
|
wire IncrementByteCnt;
|
wire IncrementByteCnt;
|
wire ControlEnd;
|
wire ControlEnd;
|
| Line 144... |
Line 149... |
TxCtrlStartFrm <= #Tp 1'b0;
|
TxCtrlStartFrm <= #Tp 1'b0;
|
else
|
else
|
if(TxUsedDataIn_q & CtrlMux)
|
if(TxUsedDataIn_q & CtrlMux)
|
TxCtrlStartFrm <= #Tp 1'b0;
|
TxCtrlStartFrm <= #Tp 1'b0;
|
else
|
else
|
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | ~TxUsedDataOutDetected))
|
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
|
TxCtrlStartFrm <= #Tp 1'b1;
|
TxCtrlStartFrm <= #Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
| Line 202... |
Line 207... |
else
|
else
|
TxUsedDataIn_q <= #Tp TxUsedDataIn;
|
TxUsedDataIn_q <= #Tp TxUsedDataIn;
|
end
|
end
|
|
|
|
|
|
|
|
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
|
|
// While sending the control frame
|
|
always @ (posedge MTxClk or posedge TxReset)
|
|
begin
|
|
if(TxReset)
|
|
BlockTxDone <= #Tp 1'b0;
|
|
else
|
|
if(TxCtrlStartFrm)
|
|
BlockTxDone <= #Tp 1'b1;
|
|
else
|
|
if(TxDoneIn)
|
|
BlockTxDone <= #Tp 1'b0;
|
|
end
|
|
|
|
|
always @ (posedge MTxClk)
|
always @ (posedge MTxClk)
|
begin
|
begin
|
ControlEnd_q <= #Tp ControlEnd;
|
ControlEnd_q <= #Tp ControlEnd;
|
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
|
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
|
end
|
end
|
