URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 166 and 167

Rev 166	Rev 167
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.36 2002/09/10 13:48:46 mohor`
	`// Reception is possible after RxPointer is read and not after BD is read. For`
	`// that reason RxBDReady is changed to RxReady.`
	`// Busy_IRQ interrupt connected. When there is no RxBD ready and frame`
	`// comes, interrupt is generated.`
	`//`
`// Revision 1.35 2002/09/10 10:35:23 mohor`	`// Revision 1.35 2002/09/10 10:35:23 mohor`
`// Ethernet debug registers removed.`	`// Ethernet debug registers removed.`
`//`	`//`
`// Revision 1.34 2002/09/08 16:31:49 mohor`	`// Revision 1.34 2002/09/08 16:31:49 mohor`
`// Async reset for WB_ACK_O removed (when core was in reset, it was`	`// Async reset for WB_ACK_O removed (when core was in reset, it was`
Line 2147...	Line 2153...
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxB_IRQ <=#Tp 1'b0;`	`RxB_IRQ <=#Tp 1'b0;`
`else`	`else`
`if(RxStatusWrite & RxIRQEn)`	`if(RxStatusWrite & RxIRQEn)`
`RxB_IRQ <=#Tp ReceivedPacketGood;`	`RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;`
`else`	`else`
`RxB_IRQ <=#Tp 1'b0;`	`RxB_IRQ <=#Tp 1'b0;`
`end`	`end`