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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 106 and 119

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Rev 106	Rev 119
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.18 2002/05/03 10:15:50 mohor`
	`// Outputs registered. Reset changed for eth_wishbone module.`
	`//`
`// Revision 1.17 2002/04/24 08:52:19 mohor`	`// Revision 1.17 2002/04/24 08:52:19 mohor`
`// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"`	`// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"`
`// bug fixed.`	`// bug fixed.`
`//`	`//`
`// Revision 1.16 2002/03/19 12:53:29 mohor`	`// Revision 1.16 2002/03/19 12:53:29 mohor`
Line 116...	Line 119...
`//`	`//`
`//`	`//`
`//`	`//`


//`define EXTERNAL_DMA // Using DMA
//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo	//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo


`// Selection of the used memory`	`// Selection of the used memory for Buffer descriptors`
//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex	//`define ETH_XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
`// specific elements.`	`// specific elements.`

//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)


`define ETH_MODER_ADR 8'h0 // 0x0	`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4	`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8	`define ETH_INT_MASK_ADR 8'h2 // 0x8

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 106 and 119