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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 203 and 211

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 203 and 211

Rev 203	Rev 211
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.23 2002/09/23 18:22:48 mohor`
	`// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet`
	`// core.`
	`//`
`// Revision 1.22 2002/09/04 18:36:49 mohor`	`// Revision 1.22 2002/09/04 18:36:49 mohor`
`// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).`	`// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).`
`//`	`//`
`// Revision 1.21 2002/08/16 22:09:47 mohor`	`// Revision 1.21 2002/08/16 22:09:47 mohor`
`// Defines for register width added. mii_rst signal in MIIMODER register`	`// Defines for register width added. mii_rst signal in MIIMODER register`
Line 140...	Line 144...

`// Selection of the used memory for Buffer descriptors`	`// Selection of the used memory for Buffer descriptors`
//`define ETH_XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex	//`define ETH_XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
`// specific elements.`	`// specific elements.`
//`define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)	//`define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
	//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS

`define ETH_MODER_ADR 8'h0 // 0x0	`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4	`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8	`define ETH_INT_MASK_ADR 8'h2 // 0x8
`define ETH_IPGT_ADR 8'h3 // 0xC	`define ETH_IPGT_ADR 8'h3 // 0xC