URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_shiftreg.v] - Diff between revs 84 and 131

Rev 84	Rev 131
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2002/03/02 21:06:01 mohor`
	`// LinkFail signal was not latching appropriate bit.`
	`//`
`// Revision 1.3 2002/01/23 10:28:16 mohor`	`// Revision 1.3 2002/01/23 10:28:16 mohor`
`// Link in the header changed.`	`// Link in the header changed.`
`//`	`//`
`// Revision 1.2 2001/10/19 08:43:51 mohor`	`// Revision 1.2 2001/10/19 08:43:51 mohor`
`// eth_timescale.v changed to timescale.v This is done because of the`	`// eth_timescale.v changed to timescale.v This is done because of the`
Line 125...	Line 128...
`ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};`	`ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
`if(LatchByte[0])`	`if(LatchByte[0])`
`begin`	`begin`
`Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};`	`Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
`if(Rgad == 5'h01)`	`if(Rgad == 5'h01)`
`LinkFail <= #Tp ~ShiftReg[2]; // because of shifting`	`LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(LatchByte[1])`	`if(LatchByte[1])`
`Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};`	`Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};`