| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/11/13 14:23:56 mohor
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// Generic memory model is used. Defines are changed for the same reason.
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//
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Revision 1.2 2001/09/24 15:02:56 mohor
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| Line 67... |
Line 70... |
//
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//
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//
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//
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//
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//
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//
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//
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//`define WISHBONE_DMA // Using DMA
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// Selection of the used memory
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// Selection of the used memory
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//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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| Line 82... |
Line 89... |
`define ETH_IPGT_ADR 6'h3 // 0xC
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`define ETH_IPGT_ADR 6'h3 // 0xC
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`define ETH_IPGR1_ADR 6'h4 // 0x10
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`define ETH_IPGR1_ADR 6'h4 // 0x10
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`define ETH_IPGR2_ADR 6'h5 // 0x14
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`define ETH_IPGR2_ADR 6'h5 // 0x14
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`define ETH_PACKETLEN_ADR 6'h6 // 0x18
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`define ETH_PACKETLEN_ADR 6'h6 // 0x18
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`define ETH_COLLCONF_ADR 6'h7 // 0x1C
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`define ETH_COLLCONF_ADR 6'h7 // 0x1C
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`define ETH_RX_BD_ADR_ADR 6'h8 // 0x20
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`define ETH_RX_BD_NUM_ADR 6'h8 // 0x20
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`define ETH_CTRLMODER_ADR 6'h9 // 0x24
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`define ETH_CTRLMODER_ADR 6'h9 // 0x24
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`define ETH_MIIMODER_ADR 6'hA // 0x28
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`define ETH_MIIMODER_ADR 6'hA // 0x28
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`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
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`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
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`define ETH_MIIADDRESS_ADR 6'hC // 0x30
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`define ETH_MIIADDRESS_ADR 6'hC // 0x30
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`define ETH_MIITX_DATA_ADR 6'hD // 0x34
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`define ETH_MIITX_DATA_ADR 6'hD // 0x34
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| Line 113... |
Line 120... |
`define ETH_MIIRX_DATA_DEF 32'h00000000
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`define ETH_MIIRX_DATA_DEF 32'h00000000
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`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR1_DEF 32'h00000000
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`define ETH_MAC_ADDR1_DEF 32'h00000000
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`define ETH_RX_BD_ADR_DEF 8'h0
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`define ETH_RX_BD_NUM_DEF 8'h80
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No newline at end of file
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No newline at end of file
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