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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 110 and 111
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| Rev 110 |
Rev 111 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2002/07/09 20:44:41 mohor
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// m_wb_cyc_o signal released after every single transfer.
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//
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// Revision 1.23 2002/05/03 10:15:50 mohor
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// Revision 1.23 2002/05/03 10:15:50 mohor
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// Outputs registered. Reset changed for eth_wishbone module.
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// Outputs registered. Reset changed for eth_wishbone module.
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//
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//
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// Revision 1.22 2002/04/24 08:52:19 mohor
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// Revision 1.22 2002/04/24 08:52:19 mohor
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// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
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// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
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| Line 885... |
Line 888... |
m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
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cyc_cleared<=#Tp 1'b0;
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cyc_cleared<=#Tp 1'b0;
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end
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end
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6'b01_10_1_0, 6'b01_11_0_1 :
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6'b01_10_0_1, 6'b01_11_0_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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