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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/09/13 18:41:45 mohor
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// Rearanged testcases
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//
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// Revision 1.7 2002/09/13 12:29:14 mohor
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// Revision 1.7 2002/09/13 12:29:14 mohor
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// Headers changed.
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// Headers changed.
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//
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//
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// Revision 1.6 2002/09/13 11:57:20 mohor
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// Revision 1.6 2002/09/13 11:57:20 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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// New testbench. Thanks to Tadej M - "The Spammer".
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`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
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`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
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/* Interrupt Source Register */
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/* Interrupt Source Register */
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`define ETH_INT_TXB 32'h00000001 /* Transmit Buffer IRQ */
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`define ETH_INT_TXB 32'h00000001 /* Transmit Buffer IRQ */
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`define ETH_INT_TXE 32'h00000002 /* Transmit Error IRQ */
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`define ETH_INT_TXE 32'h00000002 /* Transmit Error IRQ */
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`define ETH_INT_RXF 32'h00000004 /* Receive Frame IRQ */
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`define ETH_INT_RXB 32'h00000004 /* Receive Buffer IRQ */
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`define ETH_INT_RXE 32'h00000008 /* Receive Error IRQ */
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`define ETH_INT_RXE 32'h00000008 /* Receive Error IRQ */
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`define ETH_INT_BUSY 32'h00000010 /* Busy IRQ */
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`define ETH_INT_BUSY 32'h00000010 /* Busy IRQ */
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`define ETH_INT_TXC 32'h00000020 /* Transmit Control Frame IRQ */
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`define ETH_INT_TXC 32'h00000020 /* Transmit Control Frame IRQ */
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`define ETH_INT_RXC 32'h00000040 /* Received Control Frame IRQ */
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`define ETH_INT_RXC 32'h00000040 /* Received Control Frame IRQ */
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