| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.26 2003/01/22 19:40:10 tadejm
|
|
// Backup version. Not fully working.
|
|
//
|
// Revision 1.25 2002/11/27 16:21:55 mohor
|
// Revision 1.25 2002/11/27 16:21:55 mohor
|
// Full duplex control frames tested.
|
// Full duplex control frames tested.
|
//
|
//
|
// Revision 1.24 2002/11/22 17:29:42 mohor
|
// Revision 1.24 2002/11/22 17:29:42 mohor
|
// Flow control test almost finished.
|
// Flow control test almost finished.
|
| Line 468... |
Line 471... |
// test_access_to_mac_reg(0, 0); // 0 - 3
|
// test_access_to_mac_reg(0, 0); // 0 - 3
|
// test_mii(0, 17); // 0 - 17
|
// test_mii(0, 17); // 0 - 17
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
// test_mac_full_duplex_transmit(0, 23); // 0 - (21)
|
// test_mac_full_duplex_transmit(0, 23); // 0 - (21)
|
test_mac_full_duplex_transmit(8, 8); // 0 - (21)
|
test_mac_full_duplex_transmit(0, 21); // 0 - (21)
|
// test_mac_full_duplex_receive(0, 13); // 0 - 13
|
// test_mac_full_duplex_receive(2, 3); // 0 - 13
|
// test_mac_full_duplex_flow_control(0, 4); // 0 - 5 What 5 stands for ?
|
// test_mac_full_duplex_flow_control(0, 4); // 0 - 5 What 5 stands for ?
|
// 4 is executed, everything is OK
|
// 4 is executed, everything is OK
|
// test_mac_half_duplex_flow(0, 0);
|
// test_mac_half_duplex_flow(0, 0);
|
|
|
test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
| Line 4110... |
Line 4113... |
integer i1;
|
integer i1;
|
integer i2;
|
integer i2;
|
integer i3;
|
integer i3;
|
integer fail;
|
integer fail;
|
integer speed;
|
integer speed;
|
|
reg no_underrun;
|
reg frame_started;
|
reg frame_started;
|
reg frame_ended;
|
reg frame_ended;
|
reg wait_for_frame;
|
reg wait_for_frame;
|
reg [31:0] addr;
|
reg [31:0] addr;
|
reg [31:0] data;
|
reg [31:0] data;
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
reg [ 7:0] st_data;
|
reg [ 7:0] st_data;
|
reg [15:0] max_tmp;
|
reg [15:0] max_tmp;
|
reg [15:0] min_tmp;
|
reg [15:0] min_tmp;
|
integer a, b, c;
|
|
begin
|
begin
|
// MAC FULL DUPLEX TRANSMIT TEST
|
// MAC FULL DUPLEX TRANSMIT TEST
|
test_heading("MAC FULL DUPLEX TRANSMIT TEST");
|
test_heading("MAC FULL DUPLEX TRANSMIT TEST");
|
$display(" ");
|
$display(" ");
|
$display("MAC FULL DUPLEX TRANSMIT TEST");
|
$display("MAC FULL DUPLEX TRANSMIT TEST");
|
| Line 4534... |
Line 4538... |
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
|
|
repeat(5) @(posedge mtx_clk); // Wait some time so PHY stores the CRC igor
|
repeat(5) @(posedge mtx_clk); // Wait some time so PHY stores the CRC
|
|
|
// check length of a PACKET
|
// check length of a PACKET
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
| Line 6668... |
Line 6672... |
begin: fr_st1
|
begin: fr_st1
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
frame_started = 1;
|
frame_started = 1;
|
end
|
end
|
begin
|
begin
|
repeat (50) @(posedge mtx_clk); // Increased from 30 to 50 igor
|
repeat (50) @(posedge mtx_clk); // Increased from 30 to 50
|
if (num_of_frames < 5)
|
if (num_of_frames < 5)
|
begin
|
begin
|
if (frame_started == 1)
|
if (frame_started == 1)
|
begin
|
begin
|
`TIME; $display("*E Frame should NOT start!");
|
`TIME; $display("*E Frame should NOT start!");
|
| Line 6910... |
Line 6914... |
if (test_num == 8) //
|
if (test_num == 8) //
|
begin
|
begin
|
// TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
|
// TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
|
test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
|
test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
|
`TIME; $display(" TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
|
$display("(%0t) tu smo zdaj", $time);
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
// reset MAC and MII LOGIC with soft reset
|
// reset_mac;
|
// reset_mac;
|
// reset_mii;
|
// reset_mii;
|
| Line 7019... |
Line 7023... |
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
|
/*
|
|
input [6:0] tx_bd_num_start;
|
|
input [6:0] tx_bd_num_end;
|
|
input [15:0] len;
|
|
input irq;
|
|
input pad;
|
|
input crc;
|
|
input [31:0] txpnt;
|
|
*/
|
|
|
|
|
|
if (tmp_len[0] == 0) // CRC appended by 'HARDWARE'
|
if (tmp_len[0] == 0) // CRC appended by 'HARDWARE'
|
// set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, 1'b1, 1'b0, !tmp_len[1], `MEMORY_BASE);
|
|
else
|
else
|
// set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, 1'b1, 1'b0, !tmp_len[1], (`MEMORY_BASE + max_tmp));
|
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(0);
|
set_tx_bd_wrap(0);
|
end
|
end
|
else if (num_of_frames <= 9)
|
else if (num_of_frames <= 9)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0) // CRC appended by 'SOFTWARE'
|
if (tmp_len[0] == 0) // CRC appended by 'SOFTWARE'
|
set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(0);
|
set_tx_bd_wrap(0);
|
end
|
end
|
// 10 <= num_of_frames < 18 => wrap set to TX BD 3
|
// 10 <= num_of_frames < 18 => wrap set to TX BD 3
|
else if ((num_of_frames == 10) || (num_of_frames == 14))
|
else if ((num_of_frames == 10) || (num_of_frames == 14))
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 4) //
|
while (tmp_bd_num < 4)
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
| Line 7082... |
Line 7073... |
while (tmp_bd_num < 5) //
|
while (tmp_bd_num < 5) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else // when (num_of_frames == 23), (i_length == 23) and therefor i_length[0] == 1 !!!
|
else // when (num_of_frames == 23), (i_length == 23) and therefor i_length[0] == 1 !!!
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1],
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1],
|
((num_of_frames == 23) && (tmp_bd_num == 0)), 1'b1, (`MEMORY_BASE + max_tmp));
|
((num_of_frames == 23) && (tmp_bd_num == 0)), 1'b1, (`MEMORY_BASE + max_tmp));
|
|
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
| Line 7103... |
Line 7095... |
while (tmp_bd_num < 6) //
|
while (tmp_bd_num < 6) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
| Line 7123... |
Line 7115... |
while (tmp_bd_num < 7) //
|
while (tmp_bd_num < 7) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
| Line 7143... |
Line 7135... |
while (tmp_bd_num < 8) //
|
while (tmp_bd_num < 8) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
| Line 7206... |
Line 7198... |
disable fr_st2;
|
disable fr_st2;
|
end
|
end
|
end
|
end
|
end
|
end
|
join
|
join
|
|
|
|
|
// check packets larger than 4 bytes
|
// check packets larger than 4 bytes
|
if (num_of_frames >= 5)
|
if (num_of_frames >= 5)
|
begin
|
begin
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
| Line 7217... |
Line 7211... |
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
|
|
$display("(%0t) 1eth_phy.tx_len = 0x%0x, i_length = 0x%0x", $time, eth_phy.tx_len, i_length);
|
|
$display("(%0t) 1num_of_frames = 0x%0x", $time, num_of_frames);
|
|
|
|
// check length of a PACKET
|
// check length of a PACKET // Check this if it is OK igor
|
if ((eth_phy.tx_len != i_length) && (i_length[0] == 1'b0) && (num_of_frames >= 6)) // (num_of_frames >= 6) igor
|
if (num_of_frames < 6)
|
// if ((a !== b) && (b[0] == 1'b0) && (c >= 6))
|
begin
|
|
if (eth_phy.tx_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames != 23) // 6 - 53 except 23
|
|
begin
|
|
if (i_length[0] == 1'b0)
|
|
begin
|
|
if (eth_phy.tx_len != i_length)
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
else if ((eth_phy.tx_len != (i_length + 4)) && (num_of_frames != 23)) // i_length + 4 igor
|
end
|
|
end
|
|
else // num_of_frames == 23
|
|
begin
|
|
if (data[12]) // Padding
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from MAC yyy");
|
if (eth_phy.tx_len != (64))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
$display("(%0t) 2eth_phy.tx_len = 0x%0x, i_length = 0x%0x", $time, eth_phy.tx_len, i_length);
|
|
$display("(%0t) 2num_of_frames = 0x%0x", $time, num_of_frames);
|
|
//a = eth_phy.tx_len;
|
|
//b = i_length;
|
|
//c = num_of_frames;
|
|
//#1;
|
|
//$display("(%0t) 2eth_phy.tx_len = 0x%0x, i_length = 0x%0x", $time, eth_phy.tx_len, i_length);
|
|
//$display("(%0t) 2num_of_frames = 0x%0x", $time, num_of_frames);
|
|
//$display("(%0t) 3eth_phy.tx_len = 0x%0x, i_length = 0x%0x", $time, eth_phy.tx_len, i_length);
|
|
//$display("(%0t) 3num_of_frames = 0x%0x", $time, num_of_frames);
|
|
end
|
end
|
else if ((eth_phy.tx_len != (min_tmp)) && (num_of_frames == 23))
|
end
|
|
else
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from MAC zzz");
|
if (eth_phy.tx_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
end
|
|
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
begin
|
begin
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
else if (num_of_frames == 23) // i_length[0] == 1 here
|
else if (num_of_frames == 23) // i_length[0] == 1 here
|
begin
|
begin
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), (min_tmp - 4), tmp);
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
|
#1 check_tx_packet( 0, (num_of_frames * 16 + i_length), (min_tmp - i_length - 4), tmp);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
| Line 7302... |
Line 7318... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check TX buffer descriptor of a packet
|
// check TX buffer descriptor of a packet
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
|
|
if (num_of_frames >= 5)
|
if (num_of_frames >= 5)
|
begin
|
begin
|
if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
|
if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
(data[15:0] !== 16'h4000) ) // without wrap bit
|
(data[15:0] !== 16'h4000) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 1: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if ((i_length[1] == 1'b1) && (i_length[0] == 1'b0)) // interrupt not enabled
|
else if ((i_length[1] == 1'b1) && (i_length[0] == 1'b0)) // interrupt not enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h2000) && // wrap bit
|
if ( (data[15:0] !== 16'h2000) && // wrap bit
|
(data[15:0] !== 16'h0000) ) // without wrap bit
|
(data[15:0] !== 16'h0000) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 2: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if ((i_length[1] == 1'b0) && (i_length[0] == 1'b1)) // interrupt enabled
|
else if ((i_length[1] == 1'b0) && (i_length[0] == 1'b1)) // interrupt enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6800) && // wrap bit
|
if ( (data[15:0] !== 16'h6800) && // wrap bit
|
(data[15:0] !== 16'h4800) ) // without wrap bit
|
(data[15:0] !== 16'h4800) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 3: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if (num_of_frames != 23) // ((i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
|
else if (num_of_frames != 23) // ((i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h2800) && // wrap bit
|
if ( (data[15:0] !== 16'h2800) && // wrap bit
|
(data[15:0] !== 16'h0800) ) // without wrap bit
|
(data[15:0] !== 16'h0800) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 4: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else // ((num_of_frames != 23) && (i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
|
else // ((num_of_frames != 23) && (i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h3800) && // wrap bit
|
if ( (data[15:0] !== 16'h3800) && // wrap bit
|
(data[15:0] !== 16'h1800) ) // without wrap bit
|
(data[15:0] !== 16'h1800) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 5: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 7406... |
Line 7423... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (i_length == 3)
|
if (i_length == 3)
|
begin
|
begin
|
$display(" pads appending to packets is selected"); // Is this line OK? Do we have PADS? igor
|
$display(" pads appending to packets is not selected (except for 0x23)");
|
$display(" using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
|
$display(" using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
|
$display(" ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
|
$display(" ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
|
0, 3);
|
0, 3);
|
end
|
end
|
else if (i_length == 9)
|
else if (i_length == 9)
|
| Line 7726... |
Line 7743... |
begin: fr_st3
|
begin: fr_st3
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
frame_started = 1;
|
frame_started = 1;
|
end
|
end
|
begin
|
begin
|
repeat (30) @(posedge mtx_clk);
|
repeat (50) @(posedge mtx_clk);
|
|
$display("(%0t) num_of_frames = 0x%0x", $time, num_of_frames);
|
if (num_of_frames < 5)
|
if (num_of_frames < 5)
|
begin
|
begin
|
if (frame_started == 1)
|
if (frame_started == 1)
|
begin
|
begin
|
`TIME; $display("*E Frame should NOT start!");
|
`TIME; $display("*E Frame should NOT start!");
|
| Line 7740... |
Line 7758... |
else
|
else
|
begin
|
begin
|
if (frame_started == 0)
|
if (frame_started == 0)
|
begin
|
begin
|
`TIME; $display("*W Frame should start!");
|
`TIME; $display("*W Frame should start!");
|
|
#500 $stop;
|
disable fr_st3;
|
disable fr_st3;
|
end
|
end
|
end
|
end
|
end
|
end
|
join
|
join
|
| Line 7756... |
Line 7775... |
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
|
if ((num_of_frames + 4) < 64)
|
|
begin
|
|
if (eth_phy.tx_len != 64)
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
begin
|
begin
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
| Line 7959... |
Line 7990... |
test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 7996... |
Line 8024... |
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 10;
|
|
|
i_length = (max_tmp - 5);
|
i_length = (max_tmp - 5);
|
while (i_length <= (max_tmp - 3)) // (max_tmp - 4) is the limit
|
while (num_of_bd <= 3)
|
begin
|
begin
|
$display(" i_length = %0d", i_length);
|
|
// choose generating carrier sense and collision
|
|
// case (i_length[1:0])
|
|
// 2'h0: // Interrupt is generated
|
|
// begin
|
|
// Reset_tx_bd nable interrupt generation
|
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
// end
|
|
// 2'h1: // Interrupt is not generated
|
|
// begin
|
|
// set_tx_bd enable interrupt generation
|
|
// mask interrupts
|
|
// wait (wbm_working == 0);
|
|
// wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// detect carrier sense in FD and no collision
|
|
// eth_phy.carrier_sense_tx_fd_detect(1);
|
|
// eth_phy.collision(0);
|
|
// end
|
|
// 2'h2: // Interrupt is not generated
|
|
// begin
|
|
// set_tx_bd disable the interrupt generation
|
|
// unmask interrupts
|
|
// wait (wbm_working == 0);
|
|
// wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
// `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// not detect carrier sense in FD and set collision
|
|
// eth_phy.carrier_sense_tx_fd_detect(0);
|
|
// eth_phy.collision(1);
|
|
// end
|
|
// default: // 2'h3: // Interrupt is not generated
|
|
// begin
|
|
// set_tx_bd disable the interrupt generation
|
|
// mask interrupts
|
|
// wait (wbm_working == 0);
|
|
// wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// detect carrier sense in FD and set collision
|
|
// eth_phy.carrier_sense_tx_fd_detect(1);
|
|
// eth_phy.collision(1);
|
|
// end
|
|
// endcase
|
|
// first destination address on ethernet PHY
|
// first destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(0);
|
eth_phy.set_tx_mem_addr(0);
|
//
|
|
if (num_of_bd == 0)
|
if (num_of_bd == 0)
|
begin
|
begin
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
| Line 8059... |
Line 8048... |
end
|
end
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
set_tx_bd_ready(2, 2);
|
set_tx_bd_ready(2, 2);
|
|
else if (num_of_bd == 3)
|
|
begin
|
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
|
set_tx_bd_wrap(2);
|
|
set_tx_bd_ready(0, 0);
|
|
i_length = 96;
|
|
end
|
|
|
|
|
// tmp_len = i_length; // length of frame
|
|
// tmp_bd_num = 0; // TX BD number
|
|
// while (tmp_bd_num < 8) //
|
|
// begin
|
|
// // if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
|
// // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
// if (tmp_len[0] == 0)
|
|
// set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
|
// else
|
|
// set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + 2*max_tmp));
|
|
// // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
// tmp_len = tmp_len + 1;
|
|
// // set TX BD number
|
|
// tmp_bd_num = tmp_bd_num + 1;
|
|
// end
|
|
// // set wrap bit
|
|
// set_tx_bd_wrap(7);
|
|
// // set ready bit
|
|
// set_tx_bd_ready((i_length - (max_tmp - 8)), (i_length - (max_tmp - 8)));
|
|
// CHECK END OF TRANSMITION
|
// CHECK END OF TRANSMITION
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
// #1 check_tx_bd((i_length - (max_tmp - 8)), data);
|
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
// #1 check_tx_bd((i_length - (max_tmp - 8)), data);
|
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
// #1 check_tx_bd((i_length - (max_tmp - 8)), data);
|
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
$display(" eth_phy length = %0d", eth_phy.tx_len);
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
// if (eth_phy.tx_len != (i_length + 4))
|
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking in the following if statement is performed only for first and last 64 lengths
|
|
// if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
|
|
// begin
|
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
// if (i_length[0] == 0)
|
if ((i_length + 4) == 100)
|
// begin
|
check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
|
|
else if ((i_length + 4) <= max_tmp)
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
// end
|
else
|
// else
|
check_tx_packet(`MEMORY_BASE, 0, max_tmp - 4, tmp);
|
// begin
|
|
// check_tx_packet((`MEMORY_BASE + 2*max_tmp), 0, i_length, tmp);
|
|
// end
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
// if (i_length[0] == 0)
|
if ((i_length + 4) == 100)
|
|
check_tx_crc(0, 100, 1'b0, tmp); // length without CRC
|
|
else if ((i_length + 4) <= max_tmp)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
// else
|
|
// check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// end
|
|
// check WB INT signal
|
|
// if (i_length[1:0] == 2'h0)
|
|
// begin
|
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// end
|
|
// else
|
|
// begin
|
|
// if (wb_int !== 1'b0)
|
|
// begin
|
|
// `TIME; $display("*E WB INT signal should not be set");
|
|
// test_fail("WB INT signal should not be set");
|
|
// fail = fail + 1;
|
|
// end
|
|
// end
|
|
// // check TX buffer descriptor of a packet
|
|
// check_tx_bd((i_length - (max_tmp - 8)), data);
|
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
// if (i_length[1] == 1'b0) // interrupt enabled
|
|
// begin
|
|
// if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
|
|
// ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
|
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// end
|
|
// else // interrupt not enabled
|
|
// begin
|
|
// if ( ((data[15:0] !== 16'h3800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
|
|
// ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
|
|
// begin
|
|
// `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
// test_fail("TX buffer descriptor status is not correct");
|
|
// fail = fail + 1;
|
|
// end
|
|
// end
|
|
// // clear first half of 8 frames from TX buffer descriptor 0
|
|
// if (num_of_frames < 4)
|
|
// clear_tx_bd((i_length - (max_tmp - 8)), (i_length - (max_tmp - 8)));
|
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
// begin
|
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
|
begin
|
begin
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Transmit Buffer was not set");
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 8201... |
Line 8139... |
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// end
|
|
// else
|
|
// begin
|
|
// if (data !== 0)
|
|
// begin
|
|
// `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
// test_fail("Any of interrupts (except Transmit Buffer) was set");
|
|
// fail = fail + 1;
|
|
// end
|
|
// end
|
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (num_of_bd == 0)
|
if (num_of_bd == 0)
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
|
else if (num_of_bd == 3)
|
|
$display(" ->packet with length %0d sent", (104));
|
// set length (loop variable)
|
// set length (loop variable)
|
i_length = i_length + 1;
|
i_length = i_length + 1;
|
// the number of frame transmitted
|
// the number of frame transmitted
|
num_of_frames = num_of_frames + 1;
|
num_of_frames = num_of_frames + 1;
|
num_of_bd = num_of_bd + 1;
|
num_of_bd = num_of_bd + 1;
|
| Line 8260... |
Line 8192... |
test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 8291... |
Line 8220... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 100;
|
|
|
i_length = (max_tmp - 5);
|
i_length = (max_tmp - 5);
|
while (i_length <= (max_tmp - 3)) // (max_tmp - 4) is the limit
|
while (num_of_bd <= 3)
|
begin
|
begin
|
$display(" i_length = %0d", i_length);
|
|
// Reset_tx_bd nable interrupt generation
|
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
// first destination address on ethernet PHY
|
// first destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(0);
|
eth_phy.set_tx_mem_addr(0);
|
// prepare BDs
|
|
if (num_of_bd == 0)
|
if (num_of_bd == 0)
|
begin
|
begin
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
| Line 8323... |
Line 8250... |
end
|
end
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
set_tx_bd_ready(2, 2);
|
set_tx_bd_ready(2, 2);
|
|
else if (num_of_bd == 3)
|
|
begin
|
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
|
set_tx_bd_wrap(2);
|
|
set_tx_bd_ready(0, 0);
|
|
i_length = 96;
|
|
end
|
|
|
|
|
// CHECK END OF TRANSMITION
|
// CHECK END OF TRANSMITION
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
| Line 8339... |
Line 8275... |
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
|
repeat (10) @(posedge mtx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
$display(" eth_phy length = %0d", eth_phy.tx_len);
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking packet
|
|
|
// check transmitted TX packet data
|
|
if ((i_length + 4) == 100)
|
|
check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
|
|
else if ((i_length + 4) <= max_tmp)
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
|
else
|
|
check_tx_packet(`MEMORY_BASE, 0, max_tmp - 4, tmp);
|
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
|
if ((i_length + 4) == 100)
|
|
check_tx_crc(0, 100, 1'b0, tmp); // length without CRC
|
|
else if ((i_length + 4) <= max_tmp)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check TX buffer descriptor of a packet
|
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Transmit Buffer was not set");
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 8393... |
Line 8342... |
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (num_of_bd == 0)
|
if (num_of_bd == 0)
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
$display(" ->packet with length %0d sent", (i_length + 4));
|
|
else if (num_of_bd == 3)
|
|
$display(" ->packet with length %0d sent", (104));
|
// set length (loop variable)
|
// set length (loop variable)
|
i_length = i_length + 1;
|
i_length = i_length + 1;
|
// the number of frame transmitted
|
// the number of frame transmitted
|
num_of_frames = num_of_frames + 1;
|
num_of_frames = num_of_frames + 1;
|
num_of_bd = num_of_bd + 1;
|
num_of_bd = num_of_bd + 1;
|
| Line 8428... |
Line 8381... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets across changed MAXFL value at ////
|
//// Test transmit packets across changed MAXFL value at ////
|
//// 47 TX buffer decriptors ( 10Mbps ). ////
|
//// 47 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
| Line 8442... |
Line 8397... |
test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
| Line 8466... |
Line 8417... |
max_tmp = min_tmp + 53;
|
max_tmp = min_tmp + 53;
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
st_data = 8'h62;
|
st_data = 8'h62;
|
set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
|
set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
|
append_tx_crc(`MEMORY_BASE, (max_tmp - 5), 1'b0); // for first packet
|
|
// enable TX, set full-duplex mode, NO padding and NO CRC appending
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
| Line 8486... |
Line 8435... |
speed = 10;
|
speed = 10;
|
|
|
i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
|
i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
|
while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
|
while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
|
begin
|
begin
|
$display(" i_length = %0d", i_length);
|
|
// prepare packet's CRC
|
|
if (num_of_bd == 1)
|
|
append_tx_crc(`MEMORY_BASE, (max_tmp - 4), 1'b0); // for second and third packets
|
|
// Reset_tx_bd nable interrupt generation
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
| Line 8528... |
Line 8471... |
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (5) @(posedge mtx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
$display(" eth_phy length = %0d", eth_phy.tx_len);
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
| Line 8546... |
Line 8488... |
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
|
if (num_of_bd !== 2)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 8632... |
Line 8575... |
test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
| Line 8656... |
Line 8595... |
max_tmp = min_tmp + 53;
|
max_tmp = min_tmp + 53;
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
st_data = 8'h62;
|
st_data = 8'h62;
|
set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
|
set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
|
append_tx_crc(`MEMORY_BASE, (max_tmp - 5), 1'b0); // for first packet
|
|
// enable TX, set full-duplex mode, NO padding and NO CRC appending
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 100;
|
|
|
i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
|
i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
|
while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
|
while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
|
begin
|
begin
|
$display(" i_length = %0d", i_length);
|
|
// prepare packet's CRC
|
|
if (num_of_bd == 1)
|
|
append_tx_crc(`MEMORY_BASE, (max_tmp - 4), 1'b0); // for second and third packets
|
|
// Reset_tx_bd nable interrupt generation
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
| Line 8718... |
Line 8649... |
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (5) @(posedge mtx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
$display(" eth_phy length = %0d", eth_phy.tx_len);
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
| Line 8736... |
Line 8666... |
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
|
if (num_of_bd !== 2)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 8822... |
Line 8753... |
test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
|
test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 8840... |
Line 8769... |
// prepare a packet of MAXFL + 10 length
|
// prepare a packet of MAXFL + 10 length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
|
|
// change MINFL value
|
// change MINFL value
|
min_tmp = max_tmp - 177;
|
min_tmp = max_tmp - 177;
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
st_data = 8'h62;
|
st_data = 8'h62;
|
| Line 8865... |
Line 8795... |
speed = 10;
|
speed = 10;
|
|
|
i_length = (min_tmp - 5);
|
i_length = (min_tmp - 5);
|
while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
|
while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
|
begin
|
begin
|
$display(" i_length = %0d", i_length);
|
|
// Reset_tx_bd nable interrupt generation
|
// Reset_tx_bd nable interrupt generation
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 8906... |
Line 8835... |
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
$display(" eth_phy length = %0d", eth_phy.tx_len);
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
| Line 8922... |
Line 8850... |
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
|
if (num_of_bd !== 0) // First packet is padded and CRC does not match.
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
|
else
|
|
tmp = 0;
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 9006... |
Line 8937... |
begin
|
begin
|
// TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
|
// TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
|
test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
|
test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
| Line 9051... |
Line 8978... |
speed = 100;
|
speed = 100;
|
|
|
i_length = (min_tmp - 5);
|
i_length = (min_tmp - 5);
|
while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
|
while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
|
begin
|
begin
|
$display(" i_length = %0d", i_length);
|
|
// Reset_tx_bd nable interrupt generation
|
// Reset_tx_bd nable interrupt generation
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 9092... |
Line 9018... |
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
$display(" eth_phy length = %0d", eth_phy.tx_len);
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
| Line 9108... |
Line 9033... |
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
|
if (num_of_bd !== 0)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
|
else
|
|
tmp = 0;
|
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 10049... |
Line 9978... |
`TIME;
|
`TIME;
|
$display(" TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
|
$display(" TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 10086... |
Line 10012... |
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 10;
|
|
|
num_of_frames = 40; // (0..3) => start under-run on first word
|
num_of_frames = 60; // (0..3) => start under-run on first word
|
num_of_bd = 0;
|
num_of_bd = 0;
|
i_data = 3; // (3) => one BYTE read in first word - FIRST byte
|
i_data = 3; // (3) => one BYTE read in first word - FIRST byte
|
i_length = (min_tmp + 4);
|
i_length = 80;
|
while (i_length < (max_tmp - 4))
|
while (i_length < (max_tmp - 4))
|
begin
|
begin
|
// Reset_tx_bd enable interrupt generation
|
// Reset_tx_bd enable interrupt generation
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 10118... |
Line 10044... |
end
|
end
|
// frame under-run checking
|
// frame under-run checking
|
frame_started = 0;
|
frame_started = 0;
|
frame_ended = 0;
|
frame_ended = 0;
|
wait_for_frame = 0;
|
wait_for_frame = 0;
|
|
no_underrun = 0;
|
fork
|
fork
|
begin
|
begin
|
// for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
|
// for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
|
// in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
|
// in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
|
repeat ((num_of_frames[31:2] + 1'b1)) @(posedge eth_ma_wb_ack_i);
|
i = 0;
|
@(negedge eth_ma_wb_ack_i); // wait for last ACK to finish
|
while (i <= (num_of_frames[31:2] + 1))
|
|
begin
|
|
@(negedge wb_clk);
|
|
if (eth_ma_wb_ack_i)
|
|
begin
|
|
i = i + 1;
|
|
end
|
|
end
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
// wait for synchronization and some additional clocks
|
// wait for synchronization and some additional clocks
|
wait_for_frame = 1;
|
wait_for_frame = 1;
|
| Line 10138... |
Line 10072... |
disable check_fr;
|
disable check_fr;
|
end
|
end
|
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
begin
|
begin
|
disable wait_fr;
|
disable wait_fr;
|
|
if (frame_ended == 1)
|
|
begin
|
|
$display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
|
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
|
|
no_underrun = 1;
|
|
end
|
|
else
|
|
begin
|
wait (frame_ended == 1);
|
wait (frame_ended == 1);
|
|
$display("(%0t) under-run on %0d. byte",
|
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
|
|
no_underrun = 0;
|
|
end
|
end
|
end
|
repeat (2) @(posedge wb_clk);
|
repeat (2) @(posedge wb_clk);
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
| Line 10160... |
Line 10106... |
end
|
end
|
begin: check_fr
|
begin: check_fr
|
// wait for frame to start
|
// wait for frame to start
|
@(posedge MTxEn);
|
@(posedge MTxEn);
|
frame_started = 1;
|
frame_started = 1;
|
`TIME; $display(" Under-run (on %0d. byte) frame started", (num_of_frames + 1));
|
|
// wait for frame to end due to under-run
|
// wait for frame to end due to under-run
|
@(negedge MTxEn);
|
@(negedge MTxEn);
|
frame_ended = 1;
|
frame_ended = 1;
|
`TIME; $display(" Under-run frame ended");
|
|
end
|
end
|
join
|
join
|
|
|
|
repeat (5) @ (posedge mtx_clk);
|
|
|
// wait for first transmit to end, if under-run didn't happen
|
// wait for first transmit to end, if under-run didn't happen
|
if (frame_ended == 0)
|
if (frame_ended == 0)
|
begin
|
begin
|
// WAIT FOR FIRST TRANSMIT
|
// WAIT FOR FIRST TRANSMIT
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
| Line 10188... |
Line 10135... |
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// CHECK FIRST FRAME
|
// CHECK FIRST FRAME
|
// check length of a first PACKET
|
// check length of a first PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
|
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of first packet out from MAC");
|
`TIME; $display("*E Wrong length of first packet out from MAC");
|
test_fail("Wrong length of first packet out from MAC");
|
test_fail("Wrong length of first packet out from MAC");
|
| Line 10252... |
Line 10200... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
else // if (frame_ended == 1)
|
begin
|
begin
|
// CHECK FIRST FRAME
|
// CHECK FIRST FRAME
|
// check length of a first PACKET
|
// check length of a first PACKET
|
|
|
|
if (no_underrun)
|
|
begin
|
|
// CHECK FIRST FRAME, without under-run !!!
|
|
// check length of a first PACKET
|
|
tmp_len = eth_phy.tx_len;
|
|
#1;
|
|
if (tmp_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of first packet out from MAC (no under-run)");
|
|
test_fail("Wrong length of first packet out from MAC (no under-run)");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
// CHECK FIRST FRAME, on which under-run occure !!!
|
|
// check length of a first PACKET
|
tmp_len = eth_phy.tx_len_err;
|
tmp_len = eth_phy.tx_len_err;
|
#1;
|
#1;
|
if (tmp_len != (num_of_frames + (4 - i_data)))
|
if (tmp_len != ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of first packet out from MAC");
|
`TIME; $display("*E Wrong length of first packet out from MAC");
|
test_fail("Wrong length of first packet out from MAC");
|
test_fail("Wrong length of first packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
// checking first packet
|
// checking first packet
|
|
if (no_underrun)
|
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp); // only received are checked
|
|
else
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
`TIME; $display("*E Wrong data of first transmitted packet");
|
`TIME; $display("*E Wrong data of first transmitted packet");
|
test_fail("Wrong data of first transmitted packet");
|
test_fail("Wrong data of first transmitted packet");
|
| Line 10279... |
Line 10249... |
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// check TX buffer descriptor of a packet
|
// check TX buffer descriptor of a packet
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
|
if (no_underrun)
|
|
begin
|
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // under-run, wrap bit
|
|
((data[15:0] !== 16'h5800) && (num_of_bd < 1)) ) // under-run, without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
|
if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
|
((data[15:0] !== 16'h5900) && (num_of_bd < 1)) ) // under-run, without wrap bit
|
((data[15:0] !== 16'h5900) && (num_of_bd < 1)) ) // under-run, without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
if (no_underrun)
|
|
begin
|
|
if ((data & `ETH_INT_TXB) !== 2'b01)
|
|
begin
|
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_TXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
if ((data & `ETH_INT_TXE) !== 2'b10)
|
if ((data & `ETH_INT_TXE) !== 2'b10)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Transmit Buffer was not set");
|
test_fail("Interrupt Transmit Error was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_TXE)) !== 0)
|
if ((data & (~`ETH_INT_TXE)) !== 0)
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
| Line 10333... |
Line 10336... |
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// CHECK SECOND FRAME
|
// CHECK SECOND FRAME
|
// check length of a second PACKET
|
// check length of a second PACKET
|
if (frame_ended == 1'b1)
|
|
begin
|
|
`TIME; $display(" Second frame after under-run ended");
|
|
end
|
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of second packet out from MAC");
|
`TIME; $display("*E Wrong length of second packet out from MAC");
|
| Line 10403... |
Line 10402... |
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// set initial value
|
// set initial value
|
i_data = i_data - 1;
|
i_data = i_data - 1;
|
// the number of frame transmitted
|
// the number of frames transmitted
|
num_of_frames = num_of_frames + 1;
|
num_of_frames = num_of_frames + 1;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
// set length (LOOP variable)
|
// set length (LOOP variable)
|
if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
|
if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
|
i_length = (max_tmp - 4);
|
i_length = (max_tmp - 4);
|
| Line 10438... |
Line 10437... |
`TIME;
|
`TIME;
|
$display(" TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
|
$display(" TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 10475... |
Line 10471... |
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 100;
|
|
|
num_of_frames = 0; // (0..3) => start under-run on first word
|
num_of_frames = 60; // (0..3) => start under-run on first word
|
num_of_bd = 0;
|
num_of_bd = 0;
|
i_data = 3; // (3) => one BYTE read in first word - FIRST byte
|
i_data = 3; // (3) => one BYTE read in first word - FIRST byte
|
i_length = (min_tmp + 4);
|
i_length = 80;
|
while (i_length < (max_tmp - 4))
|
while (i_length < (max_tmp - 4))
|
begin
|
begin
|
// Reset_tx_bd enable interrupt generation
|
// Reset_tx_bd enable interrupt generation
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 10499... |
Line 10495... |
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
|
set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(1);
|
set_tx_bd_wrap(1);
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h2, 8'h0);
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
end
|
end
|
// frame under-run checking
|
// frame under-run checking
|
frame_started = 0;
|
frame_started = 0;
|
frame_ended = 0;
|
frame_ended = 0;
|
wait_for_frame = 0;
|
wait_for_frame = 0;
|
|
no_underrun = 0;
|
fork
|
fork
|
begin
|
begin
|
// for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
|
// for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
|
// in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
|
// in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
|
repeat ((num_of_frames[31:2] + 1'b1)) @(posedge eth_ma_wb_ack_i);
|
i = 0;
|
@(negedge eth_ma_wb_ack_i); // wait for last ACK to finish
|
while (i <= (num_of_frames[31:2] + 1))
|
|
begin
|
|
@(negedge wb_clk);
|
|
if (eth_ma_wb_ack_i)
|
|
begin
|
|
i = i + 1;
|
|
end
|
|
end
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h7, 8'hFF);
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
// wait for synchronization and some additional clocks
|
// wait for synchronization and some additional clocks
|
wait_for_frame = 1;
|
wait_for_frame = 1;
|
// wait for frame
|
// wait for frame
|
wait ((wait_for_frame == 0) || (frame_started == 1))
|
wait ((wait_for_frame == 0) || (frame_started == 1))
|
if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
|
if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
|
| Line 10527... |
Line 10531... |
disable check_fr1;
|
disable check_fr1;
|
end
|
end
|
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
begin
|
begin
|
disable wait_fr1;
|
disable wait_fr1;
|
|
if (frame_ended == 1)
|
|
begin
|
|
$display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
|
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
|
|
no_underrun = 1;
|
|
end
|
|
else
|
|
begin
|
wait (frame_ended == 1);
|
wait (frame_ended == 1);
|
|
$display("(%0t) under-run on %0d. byte",
|
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
|
|
no_underrun = 0;
|
|
end
|
end
|
end
|
repeat (2) @(posedge wb_clk);
|
repeat (2) @(posedge wb_clk);
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
|
wb_slave.cycle_response(`ACK_RESPONSE, 3'h2, 8'h0);
|
wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
end
|
end
|
begin: wait_fr1
|
begin: wait_fr1
|
wait (wait_for_frame == 1)
|
wait (wait_for_frame == 1)
|
begin
|
begin
|
// wait for synchronization and some additional clocks
|
// wait for synchronization and some additional clocks
|
| Line 10549... |
Line 10565... |
end
|
end
|
begin: check_fr1
|
begin: check_fr1
|
// wait for frame to start
|
// wait for frame to start
|
@(posedge MTxEn);
|
@(posedge MTxEn);
|
frame_started = 1;
|
frame_started = 1;
|
$display(" Under-run (on %0d. byte) frame started", (num_of_frames + 1));
|
|
// wait for frame to end due to under-run
|
// wait for frame to end due to under-run
|
@(negedge MTxEn);
|
@(negedge MTxEn);
|
frame_ended = 1;
|
frame_ended = 1;
|
$display(" Under-run frame ended");
|
|
end
|
end
|
join
|
join
|
|
|
|
repeat (5) @ (posedge mtx_clk);
|
|
|
// wait for first transmit to end, if under-run didn't happen
|
// wait for first transmit to end, if under-run didn't happen
|
if (frame_ended == 0)
|
if (frame_ended == 0)
|
begin
|
begin
|
// WAIT FOR FIRST TRANSMIT
|
// WAIT FOR FIRST TRANSMIT
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
| Line 10573... |
Line 10590... |
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (10) @(posedge wb_clk);
|
// CHECK FIRST FRAME
|
// CHECK FIRST FRAME
|
// check length of a first PACKET
|
// check length of a first PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
|
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of second packet out from MAC");
|
`TIME; $display("*E Wrong length of first packet out from MAC");
|
|
test_fail("Wrong length of first packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking first packet
|
// checking first packet
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of second transmitted packet");
|
`TIME; $display("*E Wrong data of first transmitted packet");
|
|
test_fail("Wrong data of first transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check first transmited TX packet CRC
|
// check first transmited TX packet CRC
|
check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
|
check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of second transmitted packet");
|
`TIME; $display("*E Wrong CRC of first transmitted packet");
|
|
test_fail("Wrong CRC of first transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
| Line 10638... |
Line 10659... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
|
else // if (frame_ended == 1)
|
|
begin
|
|
// CHECK FIRST FRAME
|
|
// check length of a first PACKET
|
|
|
|
if (no_underrun)
|
|
begin
|
|
// CHECK FIRST FRAME, without under-run !!!
|
|
// check length of a first PACKET
|
|
tmp_len = eth_phy.tx_len;
|
|
#1;
|
|
if (tmp_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of first packet out from MAC (no under-run)");
|
|
test_fail("Wrong length of first packet out from MAC (no under-run)");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
// CHECK FIRST FRAME, on which under-run occure !!!
|
|
// check length of a first PACKET
|
|
tmp_len = eth_phy.tx_len_err-1; // -1 because synchronization at 100 Mbps is slover then at 10 Mbps (wb_clk remains the same)
|
|
#1;
|
|
if (tmp_len != ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])))
|
|
begin
|
|
`TIME; $display("*E Wrong length of first packet out from MAC");
|
|
test_fail("Wrong length of first packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// checking first packet
|
|
if (no_underrun)
|
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp); // only received are checked
|
|
else
|
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of first transmitted packet");
|
|
test_fail("Wrong data of first transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// check TX buffer descriptor of a packet
|
|
check_tx_bd(num_of_bd, data);
|
|
if (no_underrun)
|
|
begin
|
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // under-run, wrap bit
|
|
((data[15:0] !== 16'h5800) && (num_of_bd < 1)) ) // under-run, without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
|
|
((data[15:0] !== 16'h5900) && (num_of_bd < 1)) ) // under-run, without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
if (no_underrun)
|
|
begin
|
|
if ((data & `ETH_INT_TXB) !== 2'b01)
|
|
begin
|
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_TXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if ((data & `ETH_INT_TXE) !== 2'b10)
|
|
begin
|
|
`TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Transmit Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_TXE)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
num_of_bd = num_of_bd + 1;
|
num_of_bd = num_of_bd + 1;
|
// destination address on ethernet PHY
|
// destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(0);
|
eth_phy.set_tx_mem_addr(0);
|
// WAIT FOR FIRST TRANSMIT
|
// WAIT FOR SECOND TRANSMIT
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
wait (MTxEn === 1'b1); // start first transmit
|
wait (MTxEn === 1'b1); // start first transmit
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
| Line 10662... |
Line 10799... |
// check length of a second PACKET
|
// check length of a second PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
|
`TIME; $display("*E Wrong length of second packet out from MAC");
|
test_fail("Wrong length of second packet out from MAC");
|
test_fail("Wrong length of second packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking second packet
|
// checking second packet
|
check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
|
check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong data of second transmitted packet");
|
test_fail("Wrong data of second transmitted packet");
|
test_fail("Wrong data of second transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check second transmited TX packet CRC
|
// check second transmited TX packet CRC
|
check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
|
check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong CRC of second transmitted packet");
|
test_fail("Wrong CRC of second transmitted packet");
|
test_fail("Wrong CRC of second transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
| Line 10721... |
Line 10861... |
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// set initial value
|
// set initial value
|
i_data = i_data - 1;
|
i_data = i_data - 1;
|
// the number of frame transmitted
|
// the number of frames transmitted
|
num_of_frames = num_of_frames + 1;
|
num_of_frames = num_of_frames + 1;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
// set length (LOOP variable)
|
// set length (LOOP variable)
|
if (num_of_frames == i_length + 4) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
|
if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
|
i_length = (max_tmp - 4);
|
i_length = (max_tmp - 4);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
// disable TX
|
// disable TX
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 11332... |
Line 11472... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else // interrupt enabled
|
else // interrupt enabled
|
begin
|
begin
|
if (data[15:0] !== 16'h6000)
|
if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 11716... |
Line 11856... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else // interrupt enabled
|
else // interrupt enabled
|
begin
|
begin
|
if (data[15:0] !== 16'h6000)
|
if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 17805... |
Line 17945... |
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
|
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
|
data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
|
data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
|
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
|
|
|
if (data_phy[31:0] !== data_wb[31:0])
|
if (data_phy[31:0] !== data_wb[31:0])
|
begin
|
begin
|
`TIME;
|
`TIME;
|
$display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
$display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
