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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2002/10/10 16:33:11 mohor
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// Bist added.
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//
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// Revision 1.23 2002/09/23 18:22:48 mohor
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// Revision 1.23 2002/09/23 18:22:48 mohor
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// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
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// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
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// core.
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// core.
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//
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//
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// Revision 1.22 2002/09/04 18:36:49 mohor
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// Revision 1.22 2002/09/04 18:36:49 mohor
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Line 220... |
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// Outputs are registered (uncomment when needed)
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// Outputs are registered (uncomment when needed)
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`define ETH_REGISTERED_OUTPUTS
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`define ETH_REGISTERED_OUTPUTS
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`define TX_FIFO_CNT_WIDTH 5
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// Settings for TX FIFO
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`define TX_FIFO_DEPTH 16
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`define ETH_TX_FIFO_CNT_WIDTH 5
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`define TX_FIFO_DATA_WIDTH 32
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`define ETH_TX_FIFO_DEPTH 16
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`define ETH_TX_FIFO_DATA_WIDTH 32
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`define RX_FIFO_CNT_WIDTH 5
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`define RX_FIFO_DEPTH 16
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// Settings for RX FIFO
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`define RX_FIFO_DATA_WIDTH 32
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`define ETH_RX_FIFO_CNT_WIDTH 5
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`define ETH_RX_FIFO_DEPTH 16
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`define ETH_RX_FIFO_DATA_WIDTH 32
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// Burst length
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`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
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`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
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// WISHBONE interface is Revision B3 compliant (uncomment when needed)
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//`define ETH_WISHBONE_B3
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No newline at end of file
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No newline at end of file
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