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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 21 and 29

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Rev 21	Rev 29
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/10/18 12:07:11 mohor`
	`// Status signals changed, Adress decoding changed, interrupt controller`
	`// added.`
	`//`
`// Revision 1.2 2001/09/24 15:02:56 mohor`	`// Revision 1.2 2001/09/24 15:02:56 mohor`
`// Defines changed (All precede with ETH_). Small changes because some`	`// Defines changed (All precede with ETH_). Small changes because some`
`// tools generate warnings when two operands are together. Synchronization`	`// tools generate warnings when two operands are together. Synchronization`
`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`	`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`
`// demands).`	`// demands).`
Line 63...	Line 67...
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

	`// Selection of the used memory`
	//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
	`// specific elements.`

`define ETH_FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements	//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
`// Should be cleared for the ASIC implementation`



`define ETH_MODER_ADR 6'h0 // 0x0	`define ETH_MODER_ADR 6'h0 // 0x0
`define ETH_INT_SOURCE_ADR 6'h1 // 0x4	`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
`define ETH_INT_MASK_ADR 6'h2 // 0x8	`define ETH_INT_MASK_ADR 6'h2 // 0x8

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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 21 and 29