| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.4 2001/10/18 12:07:11 mohor
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// Revision 1.4 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.3 2001/09/24 15:02:56 mohor
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// Revision 1.3 2001/09/24 15:02:56 mohor
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| Line 112... |
Line 116... |
input [31:0] wb_dat_i; // WISHBONE data input
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input [31:0] wb_dat_i; // WISHBONE data input
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output [31:0] wb_dat_o; // WISHBONE data output
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output [31:0] wb_dat_o; // WISHBONE data output
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output wb_err_o; // WISHBONE error output
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output wb_err_o; // WISHBONE error output
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// WISHBONE slave
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// WISHBONE slave
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input [31:0] wb_adr_i; // WISHBONE address input
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input [11:2] wb_adr_i; // WISHBONE address input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input wb_we_i; // WISHBONE write enable input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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| Line 241... |
Line 245... |
wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
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wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
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wire BDCs; // Buffer descriptor CS
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wire BDCs; // Buffer descriptor CS
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assign DWord = &wb_sel_i;
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assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[17] & ~wb_adr_i[16];
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[17] & wb_adr_i[16];
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10];
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assign wb_ack_o = RegCs | BDAck;
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assign wb_ack_o = RegCs | BDAck;
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assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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// Selecting the WISHBONE output data
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// Selecting the WISHBONE output data
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| Line 485... |
Line 489... |
(
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(
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.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
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.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
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.WB_DAT_O(DMA_WB_DAT_O),
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.WB_DAT_O(DMA_WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
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.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
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.WB_RD_O(wb_rd_o),
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.WB_RD_O(wb_rd_o),
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//TX
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//TX
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