| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.19 2002/02/16 14:03:44 mohor
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// Registered trimmed. Unused registers removed.
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//
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// Revision 1.18 2002/02/16 13:06:33 mohor
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// Revision 1.18 2002/02/16 13:06:33 mohor
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// EXTERNAL_DMA used instead of WISHBONE_DMA.
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// EXTERNAL_DMA used instead of WISHBONE_DMA.
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//
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//
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// Revision 1.17 2002/02/16 07:15:27 mohor
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// Revision 1.17 2002/02/16 07:15:27 mohor
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// Testbench fixed, code simplified, unused signals removed.
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// Testbench fixed, code simplified, unused signals removed.
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| Line 130... |
Line 133... |
// WISHBONE common
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// WISHBONE common
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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// WISHBONE slave
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_ack_i,
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`ifdef EXTERNAL_DMA
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`ifdef EXTERNAL_DMA
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wb_req_o, wb_nd_o, wb_rd_o,
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wb_ack_i, wb_req_o, wb_nd_o, wb_rd_o,
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`else
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`else
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// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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| Line 176... |
Line 178... |
input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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`ifdef EXTERNAL_DMA
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`ifdef EXTERNAL_DMA
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// DMA
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// DMA
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input [1:0] wb_ack_i; // DMA acknowledge input
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output wb_rd_o; // DMA restart descriptor output
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output wb_rd_o; // DMA restart descriptor output
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`else
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`else
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// WISHBONE master
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// WISHBONE master
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| Line 192... |
Line 195... |
output m_wb_stb_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
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input m_wb_ack_i;
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input m_wb_err_i;
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input m_wb_err_i;
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`endif
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`endif
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input [1:0] wb_ack_i; // DMA acknowledge input
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// Tx
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// Tx
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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