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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 80 and 95

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Rev 80 Rev 95
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.22  2002/02/26 16:59:54  mohor
 
// Small fixes for external/internal DMA missmatches.
 
//
// Revision 1.21  2002/02/26 16:21:00  mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
// Interrupts changed in the top file
// Interrupts changed in the top file
//
//
// Revision 1.20  2002/02/18 10:40:17  mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
// Small fixes.
// Small fixes.
Line 156... Line 159...
 
 
  //RX
  //RX
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
 
 
  // MIIM
  // MIIM
  mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
 
 
  int_o
  int_o
 
 
 
 
);
);
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// MII Management interface
// MII Management interface
input           md_pad_i;      // MII data input (from I/O cell)
input           md_pad_i;      // MII data input (from I/O cell)
output          mdc_pad_o;     // MII Management data clock (to PHY)
output          mdc_pad_o;     // MII Management data clock (to PHY)
output          md_pad_o;      // MII data output (to I/O cell)
output          md_pad_o;      // MII data output (to I/O cell)
output          md_padoen_o;   // MII data output enable (to I/O cell)
output          md_padoe_o;    // MII data output enable (to I/O cell)
 
 
output          int_o;         // Interrupt output
output          int_o;         // Interrupt output
 
 
wire     [7:0]  r_ClkDiv;
wire     [7:0]  r_ClkDiv;
wire            r_MiiNoPre;
wire            r_MiiNoPre;
Line 263... Line 266...
(
(
  .Clk(wb_clk_i),                         .Reset(r_MiiMRst),                  .Divider(r_ClkDiv),
  .Clk(wb_clk_i),                         .Reset(r_MiiMRst),                  .Divider(r_ClkDiv),
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
  .MdoEn(md_padoen_o),                    .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
);
 
 
 
 

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