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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 112 and 113

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Rev 112 Rev 113
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.26  2002/07/10 13:12:38  mohor
 
// Previous bug wasn't succesfully removed. Now fixed.
 
//
// Revision 1.25  2002/07/09 23:53:24  mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
// Master state machine had a bug when switching from master write to
// Master state machine had a bug when switching from master write to
// master read.
// master read.
//
//
// Revision 1.24  2002/07/09 20:44:41  mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
Line 1518... Line 1521...
  else
  else
  if(RxEn_q)
  if(RxEn_q)
    RxPointerRead <=#Tp 1'b0;
    RxPointerRead <=#Tp 1'b0;
end
end
 
 
reg BlockingIncrementRxPointer;
 
//Latching Rx buffer pointer from buffer descriptor;
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxPointer <=#Tp 32'h0;
    RxPointer <=#Tp 32'h0;
  else
  else
  if(RxEn & RxEn_q & RxPointerRead)
  if(RxEn & RxEn_q & RxPointerRead)
    RxPointer <=#Tp {ram_do[31:2], 2'h0};
    RxPointer <=#Tp {ram_do[31:2], 2'h0};
  else
  else
  if(MasterWbRX & ~BlockingIncrementRxPointer)
  if(MasterWbRX & m_wb_ack_i)
      RxPointer <=#Tp RxPointer + 3'h4; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
      RxPointer <=#Tp RxPointer + 3'h4; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
end
end
 
 
 
 
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
Line 1560... Line 1563...
end
end
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
 
    BlockingIncrementRxPointer <=#Tp 0;
 
  else
 
  if(MasterAccessFinished)
 
    BlockingIncrementRxPointer <=#Tp 0;
 
  else
 
  if(MasterWbRX)
 
    BlockingIncrementRxPointer <=#Tp 1'b1;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
  if(Reset)
    RxEn_needed <=#Tp 1'b0;
    RxEn_needed <=#Tp 1'b0;
  else
  else
  if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)
  if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)
    RxEn_needed <=#Tp 1'b1;
    RxEn_needed <=#Tp 1'b1;

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