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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 118 and 119
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| Rev 118 |
Rev 119 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.29 2002/07/20 00:41:32 mohor
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// ShiftEnded synchronization changed.
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//
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// Revision 1.28 2002/07/18 16:11:46 mohor
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// Revision 1.28 2002/07/18 16:11:46 mohor
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// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
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// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
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//
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//
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// Revision 1.27 2002/07/11 02:53:20 mohor
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// Revision 1.27 2002/07/11 02:53:20 mohor
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// RxPointer bug fixed.
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// RxPointer bug fixed.
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Line 427... |
end
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end
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assign WB_DAT_O = ram_do;
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assign WB_DAT_O = ram_do;
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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generic_spram #(8, 32) ram (
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eth_spram_256x32 bd_ram (
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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);
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);
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assign ram_ce = 1'b1;
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assign ram_ce = 1'b1;
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