| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.17 2002/03/09 16:08:45 mohor
|
|
// rx_fifo was not always cleared ok. Fixed.
|
|
//
|
// Revision 1.16 2002/03/09 13:51:20 mohor
|
// Revision 1.16 2002/03/09 13:51:20 mohor
|
// Status was not latched correctly sometimes. Fixed.
|
// Status was not latched correctly sometimes. Fixed.
|
//
|
//
|
// Revision 1.15 2002/03/08 06:56:46 mohor
|
// Revision 1.15 2002/03/08 06:56:46 mohor
|
// Big Endian problem when sending frames fixed.
|
// Big Endian problem when sending frames fixed.
|
| Line 321... |
Line 324... |
wire TxRetryPulse;
|
wire TxRetryPulse;
|
wire TxDonePulse;
|
wire TxDonePulse;
|
wire TxAbortPulse;
|
wire TxAbortPulse;
|
|
|
wire StartRxBDRead;
|
wire StartRxBDRead;
|
wire StartRxStatusWrite;
|
|
|
|
wire StartTxBDRead;
|
wire StartTxBDRead;
|
|
|
wire TxIRQEn;
|
wire TxIRQEn;
|
wire WrapTxStatusBit;
|
wire WrapTxStatusBit;
|
| Line 438... |
Line 440... |
BDWrite <=#Tp 1'b0;
|
BDWrite <=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between three stages depends on enable signals
|
// Switching between three stages depends on enable signals
|
casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
|
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
|
5'b100_1x :
|
5'b100_10, 5'b100_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
|
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
|
TxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b0;
|
ram_addr <=#Tp RxBDAddress + RxPointerRead;
|
ram_addr <=#Tp RxBDAddress + RxPointerRead;
|
| Line 455... |
Line 457... |
RxEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
ram_addr <=#Tp TxBDAddress + TxPointerRead;
|
ram_addr <=#Tp TxBDAddress + TxPointerRead;
|
ram_di <=#Tp TxBDDataIn;
|
ram_di <=#Tp TxBDDataIn;
|
end
|
end
|
5'b010_x0 :
|
5'b010_00, 5'b010_10 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
|
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
|
RxEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b0;
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
ram_di <=#Tp WB_DAT_I;
|
ram_di <=#Tp WB_DAT_I;
|
BDWrite <=#Tp BDCs & WB_WE_I;
|
BDWrite <=#Tp BDCs & WB_WE_I;
|
BDRead <=#Tp BDCs & ~WB_WE_I;
|
BDRead <=#Tp BDCs & ~WB_WE_I;
|
end
|
end
|
5'b010_x1 :
|
5'b010_01, 5'b010_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
|
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
|
ram_addr <=#Tp TxBDAddress + TxPointerRead;
|
ram_addr <=#Tp TxBDAddress + TxPointerRead;
|
ram_di <=#Tp TxBDDataIn;
|
ram_di <=#Tp TxBDDataIn;
|
end
|
end
|
5'b001_xx :
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
|
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
|
RxEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b0;
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
| Line 567... |
Line 569... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDRead <=#Tp 1'b1;
|
TxBDRead <=#Tp 1'b1;
|
else
|
else
|
if(StartTxBDRead)
|
if(StartTxBDRead & ~TxBDReady)
|
TxBDRead <=#Tp 1'b1;
|
TxBDRead <=#Tp 1'b1;
|
else
|
else
|
if(TxBDReady)
|
if(TxBDReady)
|
TxBDRead <=#Tp 1'b0;
|
TxBDRead <=#Tp 1'b0;
|
end
|
end
|
| Line 617... |
Line 619... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxBDRead <=#Tp 1'b0;
|
BlockingTxBDRead <=#Tp 1'b0;
|
else
|
else
|
if(StartTxBDRead)
|
if(StartTxBDRead & ~TxBDReady)
|
BlockingTxBDRead <=#Tp 1'b1;
|
BlockingTxBDRead <=#Tp 1'b1;
|
else
|
else
|
if(TxStartFrm_wb)
|
if(TxStartFrm_wb)
|
BlockingTxBDRead <=#Tp 1'b0;
|
BlockingTxBDRead <=#Tp 1'b0;
|
end
|
end
|
| Line 751... |
Line 753... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockReadTxDataFromMemory <=#Tp 1'b0;
|
BlockReadTxDataFromMemory <=#Tp 1'b0;
|
else
|
else
|
if(ReadTxDataFromFifo_wb)
|
if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory)
|
BlockReadTxDataFromMemory <=#Tp 1'b0;
|
BlockReadTxDataFromMemory <=#Tp 1'b0;
|
else
|
else
|
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
|
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
|
BlockReadTxDataFromMemory <=#Tp 1'b1;
|
BlockReadTxDataFromMemory <=#Tp 1'b1;
|
end
|
end
|
| Line 763... |
Line 765... |
|
|
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
|
|
assign m_wb_sel_o = 4'hf;
|
assign m_wb_sel_o = 4'hf;
|
|
reg[3:0] state;
|
|
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 776... |
Line 778... |
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
|
state <=#Tp 4'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
|
case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
|
| Line 789... |
Line 792... |
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
|
state <=#Tp 4'h1;
|
end
|
end
|
5'b00_10_0, 5'b00_10_1 :
|
5'b00_10_0, 5'b00_10_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
|
state <=#Tp 4'h2;
|
end
|
end
|
5'b10_10_1 :
|
5'b10_10_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
|
state <=#Tp 4'h3;
|
end
|
end
|
5'b01_01_1 :
|
5'b01_01_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
|
state <=#Tp 4'h4;
|
end
|
end
|
5'b10_01_1, 5'b10_11_1 :
|
5'b10_01_1, 5'b10_11_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
|
state <=#Tp 4'h5;
|
end
|
end
|
5'b01_10_1, 5'b01_11_1 :
|
5'b01_10_1, 5'b01_11_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_adr_o <=#Tp TxPointer;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
|
state <=#Tp 4'h6;
|
end
|
end
|
5'b10_00_1, 5'b01_00_1 :
|
5'b10_00_1, 5'b01_00_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
|
state <=#Tp 4'h7;
|
end
|
end
|
default: // Don't touch
|
default: // Don't touch
|
begin
|
begin
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbRX <=#Tp MasterWbRX;
|
MasterWbRX <=#Tp MasterWbRX;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
|
state <=#Tp state;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
| Line 1331... |
Line 1342... |
else
|
else
|
TxAbort_wb <=#Tp TxAbortSync1;
|
TxAbort_wb <=#Tp TxAbortSync1;
|
end
|
end
|
|
|
|
|
assign StartRxBDRead = RxStatusWrite | RxAbort;
|
assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
|
|
|
// Reading the Rx buffer descriptor
|
// Reading the Rx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDRead <=#Tp 1'b1;
|
RxBDRead <=#Tp 1'b1;
|
else
|
else
|
if(StartRxBDRead)
|
if(StartRxBDRead & ~RxBDReady)
|
RxBDRead <=#Tp 1'b1;
|
RxBDRead <=#Tp 1'b1;
|
else
|
else
|
if(RxBDReady)
|
if(RxBDReady)
|
RxBDRead <=#Tp 1'b0;
|
RxBDRead <=#Tp 1'b0;
|
end
|
end
|
| Line 1625... |
Line 1636... |
reg RxAbortSync1;
|
reg RxAbortSync1;
|
reg RxAbortSync2;
|
reg RxAbortSync2;
|
reg RxAbortSyncb1;
|
reg RxAbortSyncb1;
|
reg RxAbortSyncb2;
|
reg RxAbortSyncb2;
|
|
|
|
reg LatchedRxStartFrm;
|
|
reg SyncRxStartFrm;
|
|
reg SyncRxStartFrm_q;
|
|
wire RxFifoReset;
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedRxStartFrm <=#Tp 0;
|
|
else
|
|
if(RxStartFrm & ~SyncRxStartFrm)
|
|
LatchedRxStartFrm <=#Tp 1;
|
|
else
|
|
if(SyncRxStartFrm)
|
|
LatchedRxStartFrm <=#Tp 0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
SyncRxStartFrm <=#Tp 0;
|
|
else
|
|
if(LatchedRxStartFrm)
|
|
SyncRxStartFrm <=#Tp 1;
|
|
else
|
|
SyncRxStartFrm <=#Tp 0;
|
|
end
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
SyncRxStartFrm_q <=#Tp 0;
|
|
else
|
|
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
|
|
end
|
|
|
|
|
|
assign RxFifoReset = SyncRxStartFrm & ~SyncRxStartFrm_q;
|
|
|
|
|
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
|
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.clear(RxAbortSync2 | RxStatusWriteLatched), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
|
.empty(RxBufferEmpty)
|
.empty(RxBufferEmpty)
|
);
|
);
|
|
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
| Line 1645... |
Line 1697... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded_tck <=#Tp 1'b0;
|
ShiftEnded_tck <=#Tp 1'b0;
|
else
|
else
|
if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort)
|
if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort & ~ShiftEnded_tck)
|
ShiftEnded_tck <=#Tp 1'b1;
|
ShiftEnded_tck <=#Tp 1'b1;
|
else
|
else
|
if(ShiftEndedSync2 | RxAbort)
|
if(ShiftEnded | RxAbort)
|
ShiftEnded_tck <=#Tp 1'b0;
|
ShiftEnded_tck <=#Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 1665... |
Line 1717... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync2 <=#Tp 1'b0;
|
ShiftEndedSync2 <=#Tp 1'b0;
|
else
|
else
|
if(ShiftEndedSync1)
|
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
|
ShiftEndedSync2 <=#Tp 1'b1;
|
|
else
|
|
if(ShiftEnded)
|
|
ShiftEndedSync2 <=#Tp 1'b0;
|
|
end
|
end
|
|
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded <=#Tp 1'b0;
|
ShiftEnded <=#Tp 1'b0;
|
else
|
else
|
if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty)
|
if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
|
ShiftEnded <=#Tp 1'b1;
|
ShiftEnded <=#Tp 1'b1;
|
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
ShiftEnded <=#Tp 1'b0;
|
ShiftEnded <=#Tp 1'b0;
|
end
|
end
|
