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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 96 and 97
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| Rev 96 |
Rev 97 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.20 2002/03/25 16:19:12 mohor
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// Any address can be used for Tx and Rx BD pointers. Address does not need
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// to be aligned.
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//
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// Revision 1.19 2002/03/19 12:51:50 mohor
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// Revision 1.19 2002/03/19 12:51:50 mohor
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// Comments in Slovene language removed.
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// Comments in Slovene language removed.
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//
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//
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// Revision 1.18 2002/03/19 12:46:52 mohor
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// Revision 1.18 2002/03/19 12:46:52 mohor
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// casex changed with case, fifo reset changed.
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// casex changed with case, fifo reset changed.
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| Line 1636... |
Line 1640... |
if(Reset)
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if(Reset)
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RxByteCnt <=#Tp 2'h0;
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RxByteCnt <=#Tp 2'h0;
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else
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else
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if(ShiftEnded_tck | RxAbort)
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if(ShiftEnded_tck | RxAbort)
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RxByteCnt <=#Tp 2'h0;
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RxByteCnt <=#Tp 2'h0;
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else
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if(RxValid & RxStartFrm & RxBDReady)
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if(RxValid & RxStartFrm & RxBDReady)
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case(RxPointerLatched)
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case(RxPointerLatched)
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2'h0 : RxByteCnt <=#Tp 2'h1;
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2'h0 : RxByteCnt <=#Tp 2'h1;
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2'h1 : RxByteCnt <=#Tp 2'h2;
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2'h1 : RxByteCnt <=#Tp 2'h2;
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2'h2 : RxByteCnt <=#Tp 2'h3;
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2'h2 : RxByteCnt <=#Tp 2'h3;
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