Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
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//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.17 2002/08/16 22:23:03 mohor
|
|
// Syntax error fixed.
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|
//
|
// Revision 1.16 2002/08/16 22:14:22 mohor
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// Revision 1.16 2002/08/16 22:14:22 mohor
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// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
|
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
|
// changed from bit position 10 to 9.
|
// changed from bit position 10 to 9.
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//
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//
|
// Revision 1.15 2002/08/14 18:26:37 mohor
|
// Revision 1.15 2002/08/14 18:26:37 mohor
|
Line 283... |
Line 286... |
.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
|
.Write (MODER_Wr),
|
.Write (MODER_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
|
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
|
|
|
// INT_MASK Register
|
// INT_MASK Register
|
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF) INT_MASK
|
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF) INT_MASK
|
Line 295... |
Line 298... |
.DataIn (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
|
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
|
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
|
.Write (INT_MASK_Wr),
|
.Write (INT_MASK_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign INT_MASKOut[31:ETH_INT_MASK_WIDTH] = 0;
|
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
|
|
|
// IPGT Register
|
// IPGT Register
|
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF) IPGT
|
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF) IPGT
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGT_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_IPGT_WIDTH-1:0]),
|
.DataOut (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
|
.DataOut (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
|
.Write (IPGT_Wr),
|
.Write (IPGT_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
|
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
|
|
|
// IPGR1 Register
|
// IPGR1 Register
|
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF) IPGR1
|
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF) IPGR1
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Line 319... |
Line 322... |
.DataIn (DataIn[`ETH_IPGR1_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_IPGR1_WIDTH-1:0]),
|
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
|
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
|
.Write (IPGR1_Wr),
|
.Write (IPGR1_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
|
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
|
|
|
// IPGR2 Register
|
// IPGR2 Register
|
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF) IPGR2
|
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF) IPGR2
|
Line 331... |
Line 334... |
.DataIn (DataIn[`ETH_IPGR2_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_IPGR2_WIDTH-1:0]),
|
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
|
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
|
.Write (IPGR2_Wr),
|
.Write (IPGR2_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
|
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
|
|
|
// PACKETLEN Register
|
// PACKETLEN Register
|
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
|
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
|
Line 343... |
Line 346... |
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (PACKETLENOut),
|
.DataOut (PACKETLENOut),
|
.Write (PACKETLEN_Wr),
|
.Write (PACKETLEN_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// COLLCONF Register
|
// COLLCONF Register
|
eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0
|
eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0
|
(
|
(
|
.DataIn (DataIn[5:0]),
|
.DataIn (DataIn[5:0]),
|
.DataOut (COLLCONFOut[5:0]),
|
.DataOut (COLLCONFOut[5:0]),
|
.Write (COLLCONF_Wr),
|
.Write (COLLCONF_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign COLLCONFOut[15:6] = 0;
|
assign COLLCONFOut[15:6] = 0;
|
|
|
eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1
|
eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1
|
(
|
(
|
.DataIn (DataIn[19:16]),
|
.DataIn (DataIn[19:16]),
|
.DataOut (COLLCONFOut[19:16]),
|
.DataOut (COLLCONFOut[19:16]),
|
.Write (COLLCONF_Wr),
|
.Write (COLLCONF_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign COLLCONFOut[31:20] = 0;
|
assign COLLCONFOut[31:20] = 0;
|
|
|
// TX_BD_NUM Register
|
// TX_BD_NUM Register
|
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
|
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
|
Line 377... |
Line 380... |
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.Write (TX_BD_NUM_Wr),
|
.Write (TX_BD_NUM_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
|
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
|
|
|
// CTRLMODER Register
|
// CTRLMODER Register
|
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF) CTRLMODER2
|
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF) CTRLMODER2
|
Line 389... |
Line 392... |
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
|
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
|
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
|
.Write (CTRLMODER_Wr),
|
.Write (CTRLMODER_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
|
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
|
|
|
// MIIMODER Register
|
// MIIMODER Register
|
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF) MIIMODER
|
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF) MIIMODER
|
Line 401... |
Line 404... |
.DataIn (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
|
.Write (MIIMODER_Wr),
|
.Write (MIIMODER_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
|
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
|
|
|
// MIICOMMAND Register
|
// MIICOMMAND Register
|
eth_register #(1, 0) MIICOMMAND0
|
eth_register #(1, 0) MIICOMMAND0
|
Line 413... |
Line 416... |
.DataIn (DataIn[0]),
|
.DataIn (DataIn[0]),
|
.DataOut (MIICOMMANDOut[0]),
|
.DataOut (MIICOMMANDOut[0]),
|
.Write (MIICOMMAND_Wr),
|
.Write (MIICOMMAND_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
eth_register #(1, 0) MIICOMMAND1
|
eth_register #(1, 0) MIICOMMAND1
|
(
|
(
|
.DataIn (DataIn[1]),
|
.DataIn (DataIn[1]),
|
Line 445... |
Line 448... |
.DataIn (DataIn[4:0]),
|
.DataIn (DataIn[4:0]),
|
.DataOut (MIIADDRESSOut[4:0]),
|
.DataOut (MIIADDRESSOut[4:0]),
|
.Write (MIIADDRESS_Wr),
|
.Write (MIIADDRESS_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIADDRESSOut[7:5] = 0;
|
assign MIIADDRESSOut[7:5] = 0;
|
|
|
eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1
|
eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1
|
(
|
(
|
.DataIn (DataIn[12:8]),
|
.DataIn (DataIn[12:8]),
|
.DataOut (MIIADDRESSOut[12:8]),
|
.DataOut (MIIADDRESSOut[12:8]),
|
.Write (MIIADDRESS_Wr),
|
.Write (MIIADDRESS_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIADDRESSOut[31:13] = 0;
|
assign MIIADDRESSOut[31:13] = 0;
|
|
|
// MIITX_DATA Register
|
// MIITX_DATA Register
|
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
|
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
|
Line 468... |
Line 471... |
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.Write (MIITX_DATA_Wr),
|
.Write (MIITX_DATA_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
|
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
|
|
|
// MIIRX_DATA Register
|
// MIIRX_DATA Register
|
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
|
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
|
Line 480... |
Line 483... |
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.Write (MIIRX_DATA_Wr),
|
.Write (MIIRX_DATA_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
|
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
|
|
|
// MAC_ADDR0 Register
|
// MAC_ADDR0 Register
|
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF) MAC_ADDR0
|
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF) MAC_ADDR0
|
Line 492... |
Line 495... |
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (MAC_ADDR0Out),
|
.DataOut (MAC_ADDR0Out),
|
.Write (MAC_ADDR0_Wr),
|
.Write (MAC_ADDR0_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// MAC_ADDR1 Register
|
// MAC_ADDR1 Register
|
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF) MAC_ADDR1
|
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF) MAC_ADDR1
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.Write (MAC_ADDR1_Wr),
|
.Write (MAC_ADDR1_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
|
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
|
|
|
// RXHASH0 Register
|
// RXHASH0 Register
|
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF) RXHASH0
|
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF) RXHASH0
|
Line 515... |
Line 518... |
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (HASH0Out),
|
.DataOut (HASH0Out),
|
.Write (HASH0_Wr),
|
.Write (HASH0_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// RXHASH1 Register
|
// RXHASH1 Register
|
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF) RXHASH1
|
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF) RXHASH1
|
(
|
(
|
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (HASH1Out),
|
.DataOut (HASH1Out),
|
.Write (HASH1_Wr),
|
.Write (HASH1_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
|
|
// Reading data from registers
|
// Reading data from registers
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or
|