| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.17 2002/02/16 07:15:27 mohor
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// Testbench fixed, code simplified, unused signals removed.
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//
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// Revision 1.16 2002/02/15 13:49:39 mohor
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// Revision 1.16 2002/02/15 13:49:39 mohor
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// RxAbort is connected differently.
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// RxAbort is connected differently.
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//
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//
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// Revision 1.15 2002/02/15 11:38:26 mohor
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// Revision 1.15 2002/02/15 11:38:26 mohor
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// Changes that were lost when updating from 1.11 to 1.14 fixed.
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// Changes that were lost when updating from 1.11 to 1.14 fixed.
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| Line 126... |
Line 129... |
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// WISHBONE slave
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_ack_i,
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wb_ack_i,
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`ifdef WISHBONE_DMA
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`ifdef EXTERNAL_DMA
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wb_req_o, wb_nd_o, wb_rd_o,
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wb_req_o, wb_nd_o, wb_rd_o,
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`else
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`else
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// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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| Line 168... |
Line 171... |
input wb_we_i; // WISHBONE write enable input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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`ifdef WISHBONE_DMA
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`ifdef EXTERNAL_DMA
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// DMA
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// DMA
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output wb_rd_o; // DMA restart descriptor output
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output wb_rd_o; // DMA restart descriptor output
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`else
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`else
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| Line 565... |
Line 568... |
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// Connecting WishboneDMA module
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// Connecting WishboneDMA module
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`ifdef WISHBONE_DMA
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`ifdef EXTERNAL_DMA
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eth_wishbonedma wishbone
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eth_wishbonedma wishbone
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`else
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`else
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eth_wishbone wishbone
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eth_wishbone wishbone
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`endif
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`endif
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(
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(
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| Line 580... |
Line 583... |
.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.Reset(wb_rst_i),
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.Reset(wb_rst_i),
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`ifdef WISHBONE_DMA
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`ifdef EXTERNAL_DMA
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.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
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.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
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.WB_ACK_I(wb_ack_i),
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.WB_ACK_I(wb_ack_i),
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`else
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`else
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// WISHBONE master
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// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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| Line 610... |
Line 613... |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
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`ifdef WISHBONE_DMA
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`ifdef EXTERNAL_DMA
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`else
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`else
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.RxAbort(RxAbort),
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.RxAbort(RxAbort),
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`endif
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`endif
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
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